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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260709T024749Z
UID:3B7B2607-4361-4D82-8110-EC75E406BA3E
DTSTART;TZID=Asia/Kolkata:20260720T090000
DTEND;TZID=Asia/Kolkata:20260724T170000
DESCRIPTION:The IEEE CEDA Bangalore Chapter\, in collaboration with the IEE
 E PES Bangalore Section and the Departments of ECE and EEE\, PES Universit
 y\, is organizing a 5-day Faculty Development Programme (FDP) on &quot;VLSI Des
 ign Tape-Out Readiness: Concepts\, Tools\, AI Workflows &amp; Automation.&quot;\n\n
 This programme is designed to equip faculty members\, researchers\, and ac
 ademicians with the knowledge and practical skills required to understand 
 modern VLSI design methodologies and prepare for industry-ready tape-out w
 orkflows.\n\nThe FDP covers the complete VLSI design flow\, including digi
 tal\, analog\, and mixed-signal IC design\, RTL design\, synthesis\, stati
 c timing analysis\, physical design\, verification\, sign-off\, DFT/DFX\, 
 reliability\, and SoC integration. Participants will also gain exposure to
  emerging AI-driven VLSI workflows\, automation techniques\, and hands-on 
 training using industry-standard EDA tools.\n\nThe sessions will be delive
 red by distinguished experts from academia and the semiconductor industry\
 , providing participants with practical insights into current design pract
 ices and future trends.\n\n[]\n\nPES University\, 100 Feet\, Ring Rd\, Dwa
 raka Nagar\, Banashankari\, Bengaluru\, Karnataka\, India\, 560085
LOCATION:PES University\, 100 Feet\, Ring Rd\, Dwaraka Nagar\, Banashankari
 \, Bengaluru\, Karnataka\, India\, 560085
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:4
SUMMARY:Faculty Development Programme on VLSI Design Tape-Out Readiness: Co
 ncepts\, Tools\, AI Workflows &amp; Automation
URL;VALUE=URI:https://events.vtools.ieee.org/m/567140
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;PDq2pG_selectionAnchorContainer&quot; da
 ta-start=&quot;275&quot; data-end=&quot;571&quot;&gt;The &lt;strong data-start=&quot;279&quot; data-end=&quot;310&quot;&gt;
 IEEE CEDA Bangalore Chapter&lt;/strong&gt;\, in collaboration with the &lt;strong d
 ata-start=&quot;338&quot; data-end=&quot;368&quot;&gt;IEEE PES Bangalore Section&lt;/strong&gt; and the
  &lt;strong data-start=&quot;377&quot; data-end=&quot;423&quot;&gt;Departments of ECE and EEE\, PES 
 University&lt;/strong&gt;\, is organizing a &lt;strong data-start=&quot;441&quot; data-end=&quot;4
 86&quot;&gt;5-day Faculty Development Programme (FDP)&lt;/strong&gt; on &lt;strong data-sta
 rt=&quot;490&quot; data-end=&quot;571&quot;&gt;&quot;VLSI Design Tape-Out Readiness: Concepts\, Tools\
 , AI Workflows &amp;amp\; Automation.&quot;&lt;/strong&gt;&lt;/p&gt;\n&lt;p data-start=&quot;573&quot; data-
 end=&quot;802&quot;&gt;This programme is designed to equip faculty members\, researcher
 s\, and academicians with the knowledge and practical skills required to u
 nderstand modern VLSI design methodologies and prepare for industry-ready 
 tape-out workflows.&lt;/p&gt;\n&lt;p data-start=&quot;804&quot; data-end=&quot;1190&quot;&gt;The FDP cover
 s the complete VLSI design flow\, including digital\, analog\, and mixed-s
 ignal IC design\, RTL design\, synthesis\, static timing analysis\, physic
 al design\, verification\, sign-off\, DFT/DFX\, reliability\, and SoC inte
 gration. Participants will also gain exposure to emerging AI-driven VLSI w
 orkflows\, automation techniques\, and hands-on training using industry-st
 andard EDA tools.&lt;/p&gt;\n&lt;p data-start=&quot;1192&quot; data-end=&quot;1389&quot;&gt;The sessions w
 ill be delivered by distinguished experts from academia and the semiconduc
 tor industry\, providing participants with practical insights into current
  design practices and future trends.&lt;/p&gt;\n&lt;p style=&quot;text-align: center\;&quot; 
 data-start=&quot;1192&quot; data-end=&quot;1389&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org
 /vtools_ui/media/display/840a7419-6b9a-4302-b916-716f2647a283&quot; alt=&quot;&quot; widt
 h=&quot;500&quot; height=&quot;623&quot;&gt;&lt;/p&gt;
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