BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260710T043917Z UID:254A2F0E-E076-4798-AC86-AD38D9163712 DTSTART;TZID=Asia/Kolkata:20260404T100000 DTEND;TZID=Asia/Kolkata:20260425T170000 DESCRIPTION:The ASIC Implementation Bootcamp – From Synthesis to GDS-II T apeout was organized during the weekends of April 2026 at the Skill Lab\, K.S. School of Engineering and Management by the Department of Electronics and Communication Engineering and IEEE KSSEM Student Branch in associatio n with the IEEE CEDA Student Chapter\, KSSEM and the IEEE Education Societ y Student Chapter\, KSSEM. The program was delivered by Mr. Lalit Sahoo\, Senior Physical Design Engineer\, and aimed to provide students with pract ical exposure to ASIC Physical Design methodologies and semiconductor back end implementation workflows.\n\nThe bootcamp was designed to bridge the g ap between academic learning and industrial practices by offering hands-on training using industry-standard tools such as Cadence Virtuoso and Caden ce Innovus. The sessions focused on the complete ASIC backend design flow\ , enabling students to understand real-world semiconductor design practice s followed in the industry.\n\nThe program was conducted over four weekend s\, with each session covering a specific stage of the ASIC Physical Desig n flow.\n\nDay 1 introduced the fundamentals of ASIC design flow\, coverin g the complete semiconductor backend process from RTL specification to GDS -II TapeOut. Students were familiarized with Cadence tools\, RTL-to-Gate s ynthesis\, technology libraries\, timing constraints\, and optimization te chniques. Demonstrations were provided on synthesis flow and backend desig n environments used in the semiconductor industry.\n\nDay 2 focused on Phy sical Design inputs and Floor Planning. Students were introduced to key in put files such as Verilog netlists\, SDC\, LEF\, technology libraries\, an d TLU+ files. The session also covered floor planning concepts including d ie area estimation\, core utilization\, macro placement\, IO planning\, po wer planning\, and congestion management. Hands-on exercises were conducte d using Cadence tools to reinforce implementation concepts.\n\nDay 3 cover ed Placement\, Clock Tree Synthesis (CTS)\, and Static Timing Analysis (ST A). Topics included global placement\, legalization\, optimization techniq ues\, scan chain reordering\, and timing closure concepts. Students were a lso introduced to setup and hold analysis\, slack computation\, clock skew \, and timing optimization strategies used in ASIC backend flows.\n\nDay 4 focused on Routing\, Signoff verification\, and GDS-II generation. The se ssion included global and detailed routing\, congestion handling\, signal integrity considerations\, filler insertion\, and metal fill concepts. Sig noff checks such as DRC\, LVS\, and timing verification were also discusse d\, leading to final GDS-II Tapeout understanding. The session concluded w ith an interactive discussion on industry expectations\, career opportunit ies\, and skill development in semiconductor physical design.\n\nOverall\, the bootcamp provided comprehensive hands-on exposure to ASIC implementat ion flow\, enabling students to gain practical knowledge of backend VLSI d esign methodologies and strengthening their readiness for careers in semic onductor and VLSI industries. The resource person’s enthusiasm and selfl ess dedication to teaching were truly commendable. His advice to students – “ Take time to choose your domain\, master its skills\, and never lo ok back”-resonated deeply with the audience.\n\nSpeaker(s): Lalit Sahoo\ n\nSkill Lab\, K. S. School of Engineering and Management (KSSEM)\, No.15\ , Mallasndra\, Off. Kanakapura Road\, Bengaluru\, Karnataka\, India\, 5601 09 LOCATION:Skill Lab\, K. S. School of Engineering and Management (KSSEM)\, N o.15\, Mallasndra\, Off. Kanakapura Road\, Bengaluru\, Karnataka\, India\, 560109 ORGANIZER:avamsikrishna@ieee.org SEQUENCE:7 SUMMARY:ASIC Implementation Bootcamp – From Synthesis to GDS-II Tapeout u sing cadence Virtuoso and Innovus URL;VALUE=URI:https://events.vtools.ieee.org/m/567314 X-ALT-DESC:Description: <br /><p>The ASIC Implementation Bootcamp &ndash\; From Synthesis to GDS-II Tapeout was organized during the weekends of Apri l 2026 at the Skill Lab\, K.S. School of Engineering and Management by the Department of Electronics and Communication Engineering and IEEE KSSEM St udent Branch in association with the IEEE CEDA Student Chapter\, KSSEM and the IEEE Education Society Student Chapter\, KSSEM. The program was deliv ered by Mr. Lalit Sahoo\, Senior Physical Design Engineer\, and aimed to p rovide students with practical exposure to ASIC Physical Design methodolog ies and semiconductor backend implementation workflows.</p>\n<p><br>The bo otcamp was designed to bridge the gap between academic learning and indust rial practices by offering hands-on training using industry-standard tools such as Cadence Virtuoso and Cadence Innovus. The sessions focused on the complete ASIC backend design flow\, enabling students to understand real- world semiconductor design practices followed in the industry.</p>\n<p>The program was conducted over four weekends\, with each session covering a s pecific stage of the ASIC Physical Design flow.</p>\n<p>Day 1 introduced t he fundamentals of ASIC design flow\, covering the complete semiconductor backend process from RTL specification to GDS-II TapeOut. Students were fa miliarized with Cadence tools\, RTL-to-Gate synthesis\, technology librari es\, timing constraints\, and optimization techniques. Demonstrations were provided on synthesis flow and backend design environments used in the se miconductor industry.</p>\n<p>Day 2 focused on Physical Design inputs and Floor Planning. Students were introduced to key input files such as Verilo g netlists\, SDC\, LEF\, technology libraries\, and TLU+ files. The sessio n also covered floor planning concepts including die area estimation\, cor e utilization\, macro placement\, IO planning\, power planning\, and conge stion management. Hands-on exercises were conducted using Cadence tools to reinforce implementation concepts.</p>\n<p>Day 3 covered Placement\, Cloc k Tree Synthesis (CTS)\, and Static Timing Analysis (STA). Topics included global placement\, legalization\, optimization techniques\, scan chain re ordering\, and timing closure concepts. Students were also introduced to s etup and hold analysis\, slack computation\, clock skew\, and timing optim ization strategies used in ASIC backend flows.</p>\n<p>Day 4 focused on Ro uting\, Signoff verification\, and GDS-II generation. The session included global and detailed routing\, congestion handling\, signal integrity cons iderations\, filler insertion\, and metal fill concepts. Signoff checks su ch as DRC\, LVS\, and timing verification were also discussed\, leading to final GDS-II Tapeout understanding. The session concluded with an interac tive discussion on industry expectations\, career opportunities\, and skil l development in semiconductor physical design.</p>\n<p>Overall\, the boot camp provided comprehensive hands-on exposure to ASIC implementation flow\ , enabling students to gain practical knowledge of backend VLSI design met hodologies and strengthening their readiness for careers in semiconductor and VLSI industries. The resource person&rsquo\;s enthusiasm and selfless dedication to teaching were truly commendable. His advice to students &nda sh\; &ldquo\; Take time to choose your domain\, master its skills\, and ne ver look back&rdquo\;-resonated deeply with the audience.&nbsp\;</p>\n<tab le style="border-collapse: collapse\; width: 100%\;" border="1"><colgroup> <col style="width: 33.3009%\;"><col style="width: 33.3009%\;"><col style=" width: 33.3009%\;"></colgroup>\n<tbody>\n<tr>\n<td style="text-align: cent er\;"><img src="https://events.vtools.ieee.org/vtools_ui/media/display/f03 7416c-d1d5-4969-99bc-95edab2b6012" width="300" height="279"></td>\n<td sty le="text-align: center\;"><img src="https://events.vtools.ieee.org/vtools_ ui/media/display/a480f07c-20ee-48fc-8120-2bd759657c89" width="300" height= "281"></td>\n<td style="text-align: center\;"><img src="https://events.vto ols.ieee.org/vtools_ui/media/display/dbdb86ec-75c9-4240-806b-0d7fa35b0fb2" width="300" height="335"></td>\n</tr>\n<tr>\n<td style="text-align: cente r\;"><img src="https://events.vtools.ieee.org/vtools_ui/media/display/2ef9 e142-9939-403c-bbd3-6d185f97e26b" width="300" height="328"></td>\n<td styl e="text-align: center\;"><img src="https://events.vtools.ieee.org/vtools_u i/media/display/889ec9ee-a1f4-4d88-afd2-2532d5967210" width="330" height=" 185"></td>\n<td style="text-align: center\;"><img src="https://events.vtoo ls.ieee.org/vtools_ui/media/display/8c226ab8-9f8d-4ce4-9d69-1aa876cc00d1" width="330" height="186"></td>\n</tr>\n</tbody>\n</table> END:VEVENT END:VCALENDAR