BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260710T052102Z
UID:EF0B8971-4EC6-479E-89FF-9A304EA5A49A
DTSTART;TZID=Asia/Kolkata:20260430T110000
DTEND;TZID=Asia/Kolkata:20260430T120000
DESCRIPTION:The IEEE CEDA Student Chapter\, KLE Technological University\, 
 organized a Tech Talk on "Device to Design: Journey of Transistors" on 30 
 April 2026 at the EC Seminar Hall. The session was delivered by Ms. Rajeel
 a Deshpande\, Associate Director\, Samsung Semiconductor India Research\, 
 who shared insights into the evolution of semiconductor technology\, stand
 ard cell library development\, technology node scaling\, and modern VLSI d
 esign practices. The talk effectively connected academic concepts with rea
 l-world industry applications and concluded with an interactive Q&A sessio
 n\, providing students with valuable guidance on careers in semiconductor 
 and VLSI domains.\n\nSpeaker(s): Rajeela Deshpande\n\nECE Seminar Hall (Se
 cond Floor) Department of Electronics and Communication Engineering\, KLE 
 Technological University\, Hubballi\, Karnataka\, India\, 580031
LOCATION:ECE Seminar Hall (Second Floor) Department of Electronics and Comm
 unication Engineering\, KLE Technological University\, Hubballi\, Karnatak
 a\, India\, 580031
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:7
SUMMARY:NEXT GEN Talks – Device to Design: Journey of Transistors
URL;VALUE=URI:https://events.vtools.ieee.org/m/567320
X-ALT-DESC:Description: <br /><p>The IEEE CEDA Student Chapter\, KLE Techno
 logical University\, organized a Tech Talk on "Device to Design: Journey o
 f Transistors" on 30 April 2026 at the EC Seminar Hall. The session was de
 livered by Ms. Rajeela Deshpande\, Associate Director\, Samsung Semiconduc
 tor India Research\, who shared insights into the evolution of semiconduct
 or technology\, standard cell library development\, technology node scalin
 g\, and modern VLSI design practices. The talk effectively connected acade
 mic concepts with real-world industry applications and concluded with an i
 nteractive Q&amp\;A session\, providing students with valuable guidance on
  careers in semiconductor and VLSI domains.</p>\n<table style="border-coll
 apse: collapse\; width: 100%\;" border="1"><colgroup><col style="width: 50
 %\;"><col style="width: 50%\;"></colgroup>\n<tbody>\n<tr>\n<td><img src="h
 ttps://events.vtools.ieee.org/vtools_ui/media/display/42dd0fc9-e964-49f4-8
 b9b-d907b1b3a241" width="500" height="368"></td>\n<td><img src="https://ev
 ents.vtools.ieee.org/vtools_ui/media/display/d1ab7914-e3bf-439c-90f7-43cb5
 69d0333" width="498" height="310"></td>\n</tr>\n<tr>\n<td><img src="https:
 //events.vtools.ieee.org/vtools_ui/media/display/49e35289-4cee-4936-aaf3-1
 04efda00e0f" width="500" height="231"></td>\n<td><img src="https://events.
 vtools.ieee.org/vtools_ui/media/display/0e7f65a9-13d5-453e-8a54-454861178f
 63" width="500" height="285"></td>\n</tr>\n</tbody>\n</table>
END:VEVENT
END:VCALENDAR