BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260710T053248Z UID:6082E650-455C-45FD-8222-05749ECF736C DTSTART;TZID=Asia/Kolkata:20260513T090000 DTEND;TZID=Asia/Kolkata:20260513T160000 DESCRIPTION:Following the inauguration of the IEEE CEDA Student Chapter\, a hands-on workshop was conducted on system design using MATLAB\, Simulink\ , HDL Coder\, and HDL Verifier workflows. The workshop was led by Dr. Anan d Mukhopadhyay\, Senior Engineer in the Education Team at MathWorks India Pvt. Ltd.\, who holds a Ph.D. in Neuromorphic Computing from IIT Kharagpur and is a Senior Member of IEEE.\n\nThe session introduced participants to model-based design methodology\, automatic VHDL/Verilog code generation\, and FPGA implementation\, with live demonstrations of system modeling in Simulink and verification workflows using HDL Verifier. The workshop aimed to give students practical exposure to industry-standard Electronic Desig n Automation (EDA) tools used for FPGA and digital system development.\n\n An interactive Q&A segment allowed participants to discuss applications of MATLAB and Simulink in research and industry\, HDL code generation and ve rification techniques\, FPGA implementation challenges\, and career opport unities in VLSI\, FPGA\, and the semiconductor industry.\n\nSpeaker(s): Dr . Anand Mukhopadhyay\, Lakshmanan Balasubramanian\n\nECE Seminar Hall (Se cond Floor) Department of Electronics and Communication Engineering\, KLE Technological University\, Hubballi\, Karnataka\, India\, 580031 LOCATION:ECE Seminar Hall (Second Floor) Department of Electronics and Comm unication Engineering\, KLE Technological University\, Hubballi\, Karnatak a\, India\, 580031 ORGANIZER:avamsikrishna@ieee.org SEQUENCE:9 SUMMARY:Workshop on System Design using Simulink and HDL Coder/Verifier Wor kflows URL;VALUE=URI:https://events.vtools.ieee.org/m/567322 X-ALT-DESC:Description: <br /><p>Following the inauguration of the IEEE CED A Student Chapter\, a hands-on workshop was conducted on system design usi ng MATLAB\, Simulink\, HDL Coder\, and HDL Verifier workflows. The worksho p was led by Dr. Anand Mukhopadhyay\, Senior Engineer in the Education Tea m at MathWorks India Pvt. Ltd.\, who holds a Ph.D. in Neuromorphic Computi ng from IIT Kharagpur and is a Senior Member of IEEE.</p>\n<p><br>The sess ion introduced participants to model-based design methodology\, automatic VHDL/Verilog code generation\, and FPGA implementation\, with live demonst rations of system modeling in Simulink and verification workflows using HD L Verifier. The workshop aimed to give students practical exposure to indu stry-standard Electronic Design Automation (EDA) tools used for FPGA and d igital system development.</p>\n<p>An interactive Q&amp\;A segment allowed participants to discuss applications of MATLAB and Simulink in research a nd industry\, HDL code generation and verification techniques\, FPGA imple mentation challenges\, and career opportunities in VLSI\, FPGA\, and the s emiconductor industry.</p>\n<table style="border-collapse: collapse\; widt h: 100%\;" border="1"><colgroup><col style="width: 33.3013%\;"><col style= "width: 33.3013%\;"><col style="width: 33.3013%\;"></colgroup>\n<tbody>\n< tr>\n<td><img src="https://events.vtools.ieee.org/vtools_ui/media/display/ 2a428c8a-1ada-428e-b79d-8a191757fe31" width="330" height="248"></td>\n<td> <img src="https://events.vtools.ieee.org/vtools_ui/media/display/d5bfb126- 8ed0-4629-915c-b9552ec42aca" width="330" height="235"></td>\n<td><img src= "https://events.vtools.ieee.org/vtools_ui/media/display/598318e4-a1c0-4cdf -a91d-454a93a10c8d" width="329" height="254"></td>\n</tr>\n<tr>\n<td><img src="https://events.vtools.ieee.org/vtools_ui/media/display/c1415ce5-4ff8- 4977-a9e7-6292657cf7fb" width="332" height="230"></td>\n<td><img src="http s://events.vtools.ieee.org/vtools_ui/media/display/200bac61-c532-4e32-b065 -f0b1c8f4c773" width="327" height="246"></td>\n<td><img src="https://event s.vtools.ieee.org/vtools_ui/media/display/a2e25047-5742-4b03-964d-e4b54967 881a" width="322" height="242"></td>\n</tr>\n</tbody>\n</table> END:VEVENT END:VCALENDAR