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DTSTART:20260308T030000
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DTSTAMP:20260710T230638Z
UID:03F89B42-F0C4-490F-8BED-D76EA9799F36
DTSTART;TZID=America/Los_Angeles:20260924T113000
DTEND;TZID=America/Los_Angeles:20260924T130000
DESCRIPTION:In the past few years\, because of high-performance computing (
 HPC) driven by artificial intelligence (AI) and data centers in this AI er
 a\, packaging using glass-core substrates has been attracting lots of trac
 tion. For example\, among others\, Intel’s one-trillion-transistors appl
 ication processor with glass-core substrate is to be shipped by the end of
  2030 (announced September 2023) and TSMC’s chip-on-panel-on-substrate (
 CoPoS) with glass-core interposer is to be shipped in Q1 of 2029 (announce
 d April 2025). In this lecture\, a brief fundamental of through-glass via 
 (TGV) and redistribution-layers (RDLs) of glass packaging will be presente
 d. The advantages and disadvantages of glass\, silicon\, and organic will 
 be discussed. Panel-level packaging vs. wafer-level packaging and the pane
 l size will also be provided. Finally\, the effects of coefficient of ther
 mal expansion (CTE) of glass-core substrate on the solder joint reliabilit
 y on printed circuit board (PCB) will be presented. Some recommendations w
 ill be provided.\n\nSpeaker(s): John Lau\, \n\nSEMI World Headquarters\, 6
 73 South Milpitas Blvd\, Milpitas\, California\, United States\, 95050
LOCATION:SEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, Cal
 ifornia\, United States\, 95050
ORGANIZER:p.wesling@ieee.org
SEQUENCE:20
SUMMARY:Glass-Core Packaging and Its Reliability
URL;VALUE=URI:https://events.vtools.ieee.org/m/567440
X-ALT-DESC:Description: <br /><p><img style="float: right\;" src="https://e
 vents.vtools.ieee.org/vtools_ui/media/display/5db9c498-8449-467a-831a-ad8d
 68eb977c" width="472" height="236">In the past few years\, because of high
 -performance computing (HPC) driven by artificial intelligence (AI) and da
 ta centers in this AI era\, packaging using glass-core substrates has been
  attracting lots of traction. For example\, among others\, Intel&rsquo\;s 
 one-trillion-transistors application processor with glass-core substrate i
 s to be shipped by the end of 2030 (announced September 2023) and TSMC&rsq
 uo\;s chip-on-panel-on-substrate (CoPoS) with glass-core interposer is to 
 be shipped in Q1 of 2029 (announced April 2025). In this lecture\, a brief
  fundamental of through-glass via (TGV) and redistribution-layers (RDLs) o
 f glass packaging will be presented. The advantages and disadvantages of g
 lass\, silicon\, and organic will be discussed. Panel-level packaging vs. 
 wafer-level packaging and the panel size will also be provided. Finally\, 
 the effects of coefficient of thermal expansion (CTE) of glass-core substr
 ate on the solder joint reliability on printed circuit board (PCB) will be
  presented. Some recommendations will be provided.</p>\n<p><br><br></p>
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