BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Australia/Canberra BEGIN:DAYLIGHT DTSTART:20261004T030000 TZOFFSETFROM:+1000 TZOFFSETTO:+1100 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=10 TZNAME:AEDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20260405T020000 TZOFFSETFROM:+1100 TZOFFSETTO:+1000 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=4 TZNAME:AEST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260711T035750Z UID:F647F50A-2366-4BA1-A1A2-AE226564F0C6 DTSTART;TZID=Australia/Canberra:20260727T133000 DTEND;TZID=Australia/Canberra:20260730T143000 DESCRIPTION:IEEE Circuits & Systems 2026 Seasonal School\n\nEmerging Techno logies and Intelligent Methodologies\nfor Next-Generation Circuits and Sys tems Design\n\nAI-assisted IC design | RF and analog circuits | Quantum te chnologies | AI hardware | 6G full-duplex systems\n\nDATES : 27\, 29 and 3 0 July 2026\n\nVENUES: UTS Ultimo and WSU Parramatta\n\nLUNCH : Lunch will be provided\n\nCONTACT : xi.zhu@uts.edu.au\n\nAbout the School\n\nThis th ree-day technical school is jointly organised by the University of Technol ogy Sydney (UTS) and Western Sydney University (WSU). It brings together r esearchers\, HDR students\, early-career researchers\, academics\, and eng ineers to explore intelligent methodologies and emerging technologies that are shaping the next generation of circuits and systems design.\n\nProgra m at a Glance:\n\nMonday 27 July 2026 13:30 to 16:30 - University of Techn ology Sydney Building 11\, Room CB11.06.408\n\nProf. Jose de la Rosa: AI-D riven Optimization of Analog circuits and Systems: Application to Sigma-De lta ADCs\n\nProf. Xi “Forest” Zhu: AI-Assisted RFIC Design from Optimi sation to Implementation\n\nMr. Yuben Fang: Analog Circuit Pre-layout Synt hesis Automation through Neural Network\n\nWednesday 29/07/2026\, 10:00 to 16:00 Western Sydney University Room PC-01.7.29 161–169 Macquarie St\, Parramatta\n\nProf. Ali Mehrabi: Integrated Circuit Design using Open Sour ce EDA Tools\n\nThursday 30/07/2026\, 11:30 to 14:30 University of Technol ogy Sydney Building 11\, Room CB11.06.408\n\nProf. Jusung Kim: Energy-Effi cient and Scalable Read-out and Interconnect Electronics for Cryogenic Sup erconducting Quantum Processing Unit\n\nProf. Tara Hamilton: Exploring Har dware Architectures for Next-Generation AI\n\nDr. Anh Tuyen Le: In-band Fu ll-Duplex Technology for 6G Mobile Networks\n\nWho should attend?\n\nPostg raduate students\, early-career researchers\, academics\, engineers\, and industry practitioners working in circuits and systems\, IC design\, AI as sisted automation\, RF/mm-wave electronics\, quantum technologies\, biomed ical circuits\, and future wireless systems.\n\nFor further enquiries plea se contact : xi.zhu@uts.edu.au\n\nCo-sponsored by: IEEE New South Wales Se ction\n\nRoom: Room CB11.06.408 \, Bldg: Building 11\, \, UTS\, Ultimo\, S ydney\, New South Wales\, Australia LOCATION:Room: Room CB11.06.408 \, Bldg: Building 11\, \, UTS\, Ultimo\, Sy dney\, New South Wales\, Australia ORGANIZER:Forest Zhu <Xi.Zhu@uts.edu.au> SEQUENCE:24 SUMMARY:IEEE Circuits & Systems 2026 Seasonal School URL;VALUE=URI:https://events.vtools.ieee.org/m/567449 X-ALT-DESC:Description: <br /><p><strong>IEEE Circuits &amp\; Systems 2026 Seasonal School&nbsp\;</strong></p>\n<p><strong>Emerging Technologies and Intelligent Methodologies&nbsp\;<br>for Next-Generation Circuits and Syste ms Design&nbsp\;</strong></p>\n<p><strong>AI-assisted IC design &nbsp\;| & nbsp\;RF and analog circuits &nbsp\;| &nbsp\;Quantum technologies &nbsp\;| &nbsp\;AI hardware &nbsp\;| &nbsp\;6G full-duplex systems</strong></p>\n< p><strong>DATES : 27\, 29 and 30 July 2026&nbsp\;</strong></p>\n<p><strong >VENUES: UTS Ultimo and WSU Parramatta&nbsp\;</strong></p>\n<p><strong>LUN CH : Lunch will be provided&nbsp\;</strong></p>\n<p><strong>CONTACT : <a h ref="mailto:xi.zhu@uts.edu.au">xi.zhu@uts.edu.au</a></strong></p>\n<p><str ong>About the School&nbsp\;<br>&nbsp\;<br>This three-day technical school is jointly organised by the University of Technology Sydney (UTS) and West ern Sydney University (WSU). It brings together researchers\, HDR students \, early-career researchers\, academics\, and engineers to explore intelli gent methodologies and emerging technologies that are shaping the next gen eration of circuits and systems design.&nbsp\;</strong></p>\n<p><strong>Pr ogram at a Glance:</strong></p>\n<p><strong>Monday 27 July 2026 13:30 to 1 6:30 - University of Technology Sydney Building 11\, Room CB11.06.408&nbsp \;</strong></p>\n<p><strong>Prof. Jose de la Rosa: AI-Driven Optimization of Analog circuits and Systems: Application to Sigma-Delta ADCs&nbsp\;<br> &nbsp\;<br>Prof. Xi &ldquo\;Forest&rdquo\; Zhu: AI-Assisted RFIC Design fr om Optimisation to Implementation&nbsp\;<br>&nbsp\;<br>Mr. Yuben Fang: Ana log Circuit Pre-layout Synthesis Automation through Neural Network</strong ></p>\n<p><strong>Wednesday 29/07/2026\,&nbsp\;10:00 to 16:00 Western Sydn ey University Room PC-01.7.29 161&ndash\;169 Macquarie St\, Parramatta</st rong></p>\n<p><strong>Prof. Ali Mehrabi: Integrated Circuit Design using O pen Source EDA Tools&nbsp\;</strong></p>\n<p><strong>Thursday 30/07/2026\, 11:30 to 14:30 University of Technology Sydney Building 11\, Room CB11.06 .408&nbsp\;</strong></p>\n<p><strong>Prof. Jusung Kim: Energy-Efficient an d Scalable Read-out and Interconnect Electronics for Cryogenic Superconduc ting Quantum Processing Unit&nbsp\;<br>&nbsp\;<br>Prof. Tara Hamilton: Exp loring Hardware Architectures for Next-Generation AI&nbsp\;<br>&nbsp\;<br> Dr. Anh Tuyen Le: In-band Full-Duplex Technology for 6G Mobile Networks&nb sp\;</strong></p>\n<p><strong>Who should attend?&nbsp\;<br>&nbsp\;<br>Post graduate students\, early-career researchers\, academics\, engineers\, and industry practitioners working in circuits and systems\, IC design\, AI a ssisted automation\, RF/mm-wave electronics\, quantum technologies\, biome dical circuits\, and future wireless systems.&nbsp\;</strong></p>\n<p><str ong>For further enquiries please contact :&nbsp\;<a href="mailto:xi.zhu@ut s.edu.au">xi.zhu@uts.edu.au</a>&nbsp\;</strong></p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR