BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260714T025705Z UID:B83C8403-A79C-4D87-B18B-B823FCB63D6B DTSTART;TZID=Asia/Kolkata:20260227T103000 DTEND;TZID=Asia/Kolkata:20260227T123000 DESCRIPTION:An Expert Session on 'VLSI Design and Test' was organized by th e Department of Electronics and Communication Engineering\, Dayananda Saga r University\, in association with the IEEE DSU Student Branch and IEEE CE DA DSU Student Branch Chapter. The session was delivered by Dr. Ravikumar CP\, Chief Learning Officer\, Vinyanatech. The expert provided an overview of VLSI design and testing roles\, explained the complete VLSI design flo w\, discussed verification and validation methodologies\, and highlighted the technical competencies expected by the semiconductor industry. The ses sion concluded with an interactive question-and-answer session where parti cipants clarified career opportunities\, design methodologies\, and indust ry expectations in VLSI. The event significantly enhanced participants' un derstanding of semiconductor design and encouraged students to pursue care ers in the VLSI domain.\n\nSpeaker(s): Ravikumar CP\n\nAgenda: \n10:00–1 0:30 AM : Registration\n10:30–10:40 AM : Welcome Address\n10:40–12:00 PM : Expert Session by Dr. Ravikumar CP\n12:00–12:20 PM : Interactive Q& A\n12:20–12:30 PM : Vote of Thanks\n\nVLSI Lab 308\, Department of ECE\, School of Engineering\, Dayananda Sagar University\, Bangalore\, Karnatak a\, India\, 560111 LOCATION:VLSI Lab 308\, Department of ECE\, School of Engineering\, Dayanan da Sagar University\, Bangalore\, Karnataka\, India\, 560111 ORGANIZER:avamsikrishna@ieee.org SEQUENCE:8 SUMMARY:Expert Session on VLSI Design and Test URL;VALUE=URI:https://events.vtools.ieee.org/m/567814 X-ALT-DESC:Description: <br /><p><span lang="EN-US" style="font-size: 11.0p t\; line-height: 115%\; font-family: 'Cambria'\,serif\; mso-ascii-theme-fo nt: minor-latin\; mso-fareast-font-family: 'MS Mincho'\; mso-fareast-theme -font: minor-fareast\; mso-hansi-theme-font: minor-latin\; mso-bidi-font-f amily: Arial\; mso-bidi-theme-font: minor-bidi\; mso-ansi-language: EN-US\ ; mso-fareast-language: EN-US\; mso-bidi-language: AR-SA\;">An Expert Sess ion on 'VLSI Design and Test' was organized by the Department of Electroni cs and Communication Engineering\, Dayananda Sagar University\, in associa tion with the IEEE DSU Student Branch and IEEE CEDA DSU Student Branch Cha pter. The session was delivered by Dr. Ravikumar CP\, Chief Learning Offic er\, Vinyanatech. The expert provided an overview of VLSI design and testi ng roles\, explained the complete VLSI design flow\, discussed verificatio n and validation methodologies\, and highlighted the technical competencie s expected by the semiconductor industry. The session concluded with an in teractive question-and-answer session where participants clarified career opportunities\, design methodologies\, and industry expectations in VLSI. The event significantly enhanced participants' understanding of semiconduc tor design and encouraged students to pursue careers in the VLSI domain.</ span></p>\n<p style="text-align: center\;"><span lang="EN-US" style="font- size: 11.0pt\; line-height: 115%\; font-family: 'Cambria'\,serif\; mso-asc ii-theme-font: minor-latin\; mso-fareast-font-family: 'MS Mincho'\; mso-fa reast-theme-font: minor-fareast\; mso-hansi-theme-font: minor-latin\; mso- bidi-font-family: Arial\; mso-bidi-theme-font: minor-bidi\; mso-ansi-langu age: EN-US\; mso-fareast-language: EN-US\; mso-bidi-language: AR-SA\;"><im g src="https://events.vtools.ieee.org/vtools_ui/media/display/1de63315-6a3 7-47f4-b919-aeadea401b43" width="581" height="271"></span></p><br /><br /> Agenda: <br /><p class="MsoNormal"><span lang="EN-US">10:00&ndash\;10:30 A M : Registration<br>10:30&ndash\;10:40 AM : Welcome Address<br>10:40&ndash \;12:00 PM : Expert Session by Dr. Ravikumar CP<br>12:00&ndash\;12:20 PM : Interactive Q&amp\;A<br>12:20&ndash\;12:30 PM : Vote of Thanks</span></p> END:VEVENT END:VCALENDAR