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DTSTAMP:20260720T175852Z
UID:826C4B3F-FF13-46BC-808D-29F911FAD25B
DTSTART;TZID=America/Sao_Paulo:20260807T100000
DTEND;TZID=America/Sao_Paulo:20260807T120000
DESCRIPTION:This talk presents recent advances in the design and deployment
  of fault-tolerant RISC-V processors and fault-tolerant AI engines impleme
 nted on SRAM-based FPGAs targeting Earth Observation and other mission-cri
 tical systems. The presentation discusses architectural and system-level t
 echniques to mitigate soft errors\, including modular and distributed redu
 ndancy\, selective hardening\, error detection and correction mechanisms\,
  configuration memory scrubbing\, and resilience-aware design methodologie
 s. Particular emphasis is placed on open RISC-V soft-cores and AI accelera
 tors for on-board inference\, highlighting trade-offs between reliability\
 , performance\, power\, and resource utilization.\n\nSpeaker(s): Fernanda 
 Kastensmidt\n\nRoom: bloco H\, sala 322\, Centro de Tecnologia da UFRJ\, C
 idade Universitária\, Centro de Tecnologia\, Rio de Janeiro\, Rio de Jane
 iro\, Brazil\, 21941972
LOCATION:Room: bloco H\, sala 322\, Centro de Tecnologia da UFRJ\, Cidade U
 niversitária\, Centro de Tecnologia\, Rio de Janeiro\, Rio de Janeiro\, B
 razil\, 21941972
ORGANIZER:fabian@coppe.ufrj.br
SEQUENCE:264
SUMMARY:IEEE CASS Rio Chapter Lecture – Using Fault Tolerant RISC-V Proce
 ssors and Fault Tolerant AI engines into FPGAs for Earth Observation and o
 ther High Reliable Applications
URL;VALUE=URI:https://events.vtools.ieee.org/m/568252
X-ALT-DESC:Description: <br /><p>This talk presents recent advances in the 
 design and deployment of fault-tolerant RISC-V processors and fault-tolera
 nt AI engines implemented on SRAM-based FPGAs targeting Earth Observation 
 and other mission-critical systems. The presentation discusses architectur
 al and system-level techniques to mitigate soft errors\, including modular
  and distributed redundancy\, selective hardening\, error detection and co
 rrection mechanisms\, configuration memory scrubbing\, and resilience-awar
 e design methodologies. Particular emphasis is placed on open RISC-V soft-
 cores and AI accelerators for on-board inference\, highlighting trade-offs
  between reliability\, performance\, power\, and resource utilization.</p>
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