BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260722T011137Z UID:D89A8501-E753-4972-AC78-214C2F1AB94C DTSTART;TZID=America/Los_Angeles:20260731T110000 DTEND;TZID=America/Los_Angeles:20260731T120000 DESCRIPTION:With the increasing demands for higher signal speeds coupled wi th the need for decreasing feature sizes\, interconnect related signal int egrity effects such as delay\, distortion\, reflections\, crosstalk\, grou nd bounce and electromagnetic interference have become the dominant factor s limiting the performance of high-speed systems. These effects can be div erse and can seriously impact the design performance at all hierarchical l evels including integrated circuits\, printed circuit boards\, multi-chip modules and backplanes. This talk provides a comprehensive approach for un derstanding the multidisciplinary problem of signal integrity: issues/mode ling/analysis in high-speed designs.\n\nSpeaker(s): Ramachandra\n\nRoom: H enry Booker Room\, Bldg: Jacobs Hall\, 9736 Engineers Ln\, La Jolla\, CA 9 2093\, San Diego\, California\, United States LOCATION:Room: Henry Booker Room\, Bldg: Jacobs Hall\, 9736 Engineers Ln\, La Jolla\, CA 92093\, San Diego\, California\, United States ORGANIZER:nkoripally@ucsd.edu SEQUENCE:16 SUMMARY:DL - Emerging High-Speed Nanoscale Interconnect Issues and Modellin g Challenges URL;VALUE=URI:https://events.vtools.ieee.org/m/569006 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\;"><span style="font-size: 12.0pt\; line-height: 115%\;">With the incre asing demands for higher signal speeds coupled with the need for decreasin g feature sizes\, interconnect related signal integrity effects such as de lay\, distortion\, reflections\, crosstalk\, ground bounce and electromagn etic interference have become the dominant factors limiting the performanc e of high-speed systems. These effects can be diverse and can seriously im pact the design performance at all hierarchical levels including integrate d circuits\, printed circuit boards\, multi-chip modules and backplanes. T his talk provides a comprehensive approach for understanding the multidisc iplinary problem of signal integrity: issues/modeling/analysis in high-spe ed designs.</span></p> END:VEVENT END:VCALENDAR