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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
DTSTART:19910915T010000
TZOFFSETFROM:+0900
TZOFFSETTO:+0800
TZNAME:CST
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BEGIN:VEVENT
DTSTAMP:20260723T092318Z
UID:9481C3D2-DFED-4F13-A17A-AFDDDC9D5048
DTSTART;TZID=Asia/Shanghai:20260727T100000
DTEND;TZID=Asia/Shanghai:20260727T110000
DESCRIPTION:As hardware systems continue to scale in complexity—from high
 -level synthesis to chiplet-based and 3D architectures—architectural inn
 ovation is increasingly constrained by slow\, rigid\, and fragmented desig
 n tools. In this talk\, I introduce the Agile Hardware Kitchen\, a suite o
 f open-source tools developed by the SHARC Lab to enable fast\, accurate\,
  and scalable hardware architecture exploration. The talk highlights OmniS
 im\, which provides near-C-speed simulation with RTL-level timing accuracy
  for complex HLS designs\; LaZagna\, an end-to-end framework for exploring
  physically realizable 3D FPGA architectures from architectural specificat
 ion to RTL and bitstream generation\; Omelet\, a packaging-aware 2.5D/3D c
 hiplet system interconnect simulator to provide high-fidelity early-stage 
 design space exploration\; and open infrastructures that support reproduci
 ble and ML-driven HLS research. Together\, these efforts aim to lower the 
 barrier to hardware architecture research\, accelerate design iteration\, 
 and enable a more open and agile future for computing systems.\n\nVirtual:
  https://events.vtools.ieee.org/m/569191
LOCATION:Virtual: https://events.vtools.ieee.org/m/569191
ORGANIZER:cedar@ieee.org
SEQUENCE:4
SUMMARY:Agile Hardware Kitchen Tools for Architecture Innovation
URL;VALUE=URI:https://events.vtools.ieee.org/m/569191
X-ALT-DESC:Description: <br /><p><span lang="EN-US" style="font-size: 11.0p
 t\; mso-bidi-font-size: 12.0pt\; line-height: 115%\; font-family: 等线\;
  mso-ascii-theme-font: minor-latin\; mso-fareast-theme-font: minor-fareast
 \; mso-hansi-theme-font: minor-latin\; mso-bidi-font-family: 'Times New Ro
 man'\; mso-bidi-theme-font: minor-bidi\; mso-ansi-language: EN-US\; mso-fa
 reast-language: ZH-CN\; mso-bidi-language: AR-SA\;">As hardware systems co
 ntinue to scale in complexity</span><span style="font-size: 11.0pt\; mso-b
 idi-font-size: 12.0pt\; line-height: 115%\; font-family: 等线\; mso-asci
 i-theme-font: minor-latin\; mso-fareast-theme-font: minor-fareast\; mso-ha
 nsi-theme-font: minor-latin\; mso-bidi-font-family: 'Times New Roman'\; ms
 o-bidi-theme-font: minor-bidi\; mso-ansi-language: EN-US\; mso-fareast-lan
 guage: ZH-CN\; mso-bidi-language: AR-SA\;">&mdash\;<span lang="EN-US">from
  high-level synthesis to chiplet-based and 3D architectures</span>&mdash\;
 <span lang="EN-US">architectural innovation is increasingly constrained by
  slow\, rigid\, and fragmented design tools. In this talk\, I introduce th
 e Agile Hardware Kitchen\, a suite of open-source tools developed by the S
 HARC Lab to enable fast\, accurate\, and scalable hardware architecture ex
 ploration. The talk highlights OmniSim\, which provides near-C-speed simul
 ation with RTL-level timing accuracy for complex HLS designs\; LaZagna\, a
 n end-to-end framework for exploring physically realizable 3D FPGA archite
 ctures from architectural specification to RTL and bitstream generation\; 
 Omelet\, a packaging-aware 2.5D/3D chiplet system interconnect simulator t
 o provide high-fidelity early-stage design space exploration\; and open in
 frastructures that support reproducible and ML-driven HLS research. Togeth
 er\, these efforts aim to lower the barrier to hardware architecture resea
 rch\, accelerate design iteration\, and enable a more open and agile futur
 e for computing systems.</span></span></p>
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