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DTSTART;TZID=America/New_York:20260727T133000
DTEND;TZID=America/New_York:20260727T143000
DESCRIPTION:Title: Hardware Acceleration for Post-Quantum Cryptography:  Al
 gorithmic Derivation and Architectural Innovation\nSpeaker: Dr. Jiafeng (H
 arvest) Xie\, Associate Professor\nDepartment of Electrical and Computer E
 ngineering\, Villanova University\n\nDate and Time:  Monday\, July 27\, 20
 26\, 1:30-2:30 PM\nLocation: George Mason University\, ENGR 3507\, 4511 Pa
 triot Cir\, Fairfax\, VA 22030\n\nAbstract: Post-quantum cryptography (PQC
 ) has drawn significant attention from various communities recently\, as t
 he existing public-key cryptosystems\, such as Rivest Shamir Adleman (RSA)
  and Elliptic Curve Cryptography (ECC)\, are proven to be vulnerable to la
 rge-scale quantum computers executing Shor’s algorithm. The National Ins
 titute of Standards and Technology (NIST) has already begun the PQC standa
 rdization process\, and hardware acceleration for PQC algorithms is one of
  the most recent areas of focus. In this talk\, I will follow this trend b
 y introducing several interesting methods to accelerate PQC algorithms on 
 the hardware platform. Specifically\, this talk will present hardware impl
 ementation methods from both algorithmic derivation and architectural inno
 vation perspectives. Implementation techniques for specific NIST-selected 
 PQC schemes are also covered in this talk. I hope this talk will facilitat
 e additional research to support PQC standardization and further developme
 nt.\n\nRoom: ENGR 3507\, Bldg: Engineering Building\, George Mason Univers
 ity\, \, 4511 Patriot Cir\, Fairfax\, VA 22030\, Fairfax\, Virginia\, Unit
 ed States\, 22030
LOCATION:Room: ENGR 3507\, Bldg: Engineering Building\, George Mason Univer
 sity\, \, 4511 Patriot Cir\, Fairfax\, VA 22030\, Fairfax\, Virginia\, Uni
 ted States\, 22030
ORGANIZER:kafi@ieee.org
SEQUENCE:26
SUMMARY:Hardware Acceleration for Post-Quantum Cryptography: Algorithmic De
 rivation and Architectural Innovation
URL;VALUE=URI:https://events.vtools.ieee.org/m/569351
X-ALT-DESC:Description: &lt;br /&gt;&lt;div class=&quot;x_elementToProof&quot;&gt;&lt;strong data-ol
 k-copy-source=&quot;MessageBody&quot;&gt;Title:&amp;nbsp\; Hardware Acceleration for Post-Q
 uantum Cryptography: &lt;/strong&gt;&amp;nbsp\;&lt;strong&gt;Algorithmic Derivation&amp;nbsp\;
 and&amp;nbsp\;Architectural Innovation&lt;/strong&gt;&lt;/div&gt;\n&lt;div class=&quot;x_elementTo
 Proof&quot;&gt;&lt;strong&gt;Speaker: &lt;/strong&gt;Dr. Jiafeng (Harvest) Xie\,&amp;nbsp\;Associa
 te Professor&lt;/div&gt;\n&lt;div class=&quot;x_elementToProof&quot;&gt;&amp;nbsp\; &amp;nbsp\; &amp;nbsp\; 
 &amp;nbsp\; &amp;nbsp\; &amp;nbsp\; &amp;nbsp\; Department of Electrical and Computer Engi
 neering\, Villanova University&lt;/div&gt;\n&lt;div class=&quot;x_elementToProof&quot;&gt;&amp;nbsp\
 ;&lt;/div&gt;\n&lt;div class=&quot;x_elementToProof&quot;&gt;&lt;strong&gt;Date and Time:&amp;nbsp\;&lt;/stro
 ng&gt; Monday\, July 27\, 2026\, 1:30-2:30 PM&lt;/div&gt;\n&lt;div class=&quot;x_elementToP
 roof&quot;&gt;&lt;strong&gt;Location: &lt;/strong&gt;George Mason University\, ENGR 3507\,&amp;nbs
 p\;4511 Patriot Cir\, Fairfax\, VA 22030&lt;/div&gt;\n&lt;div class=&quot;x_elementToPro
 of&quot;&gt;&amp;nbsp\;&lt;/div&gt;\n&lt;div class=&quot;x_elementToProof&quot;&gt;&lt;strong data-olk-copy-sou
 rce=&quot;MessageBody&quot;&gt;Abstract:&lt;/strong&gt; Post-quantum cryptography (PQC) has d
 rawn significant attention from various communities recently\, as the exis
 ting public-key cryptosystems\, such as Rivest Shamir Adleman (RSA) and El
 liptic Curve Cryptography (ECC)\, are proven to be vulnerable to large-sca
 le quantum computers executing Shor&amp;rsquo\;s algorithm. The National Insti
 tute of Standards and Technology (NIST) has already begun the PQC standard
 ization process\, and hardware acceleration for PQC algorithms is one of t
 he most recent areas of focus. In this talk\, I will follow this trend by 
 introducing several interesting methods to accelerate PQC algorithms on th
 e hardware platform. Specifically\, this talk will present hardware implem
 entation methods from both algorithmic derivation and architectural innova
 tion perspectives. Implementation techniques for specific NIST-selected PQ
 C schemes are also covered in this talk.&amp;nbsp\;I hope this talk will facil
 itate additional research to support PQC standardization and further devel
 opment.&lt;/div&gt;
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