BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Taipei
BEGIN:STANDARD
DTSTART:19790930T230000
TZOFFSETFROM:+0900
TZOFFSETTO:+0800
TZNAME:CST
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BEGIN:VEVENT
DTSTAMP:20260924T165054Z
UID:8E079BC0-8AEA-417F-9898-C538D4638B45
DTSTART;TZID=Asia/Taipei:20261020T155000
DTEND;TZID=Asia/Taipei:20261020T162000
DESCRIPTION:Artificial intelligence (AI) infrastructure is moving from acce
 lerator-level optimization toward validated AI-factory capacity. In this r
 egime\, peak silicon performance is necessary but insufficient: deployable
  capacity depends on the coupled behavior of silicon\, heterogeneous packa
 ge\, substrate\, board\, rack\, liquid-cooling loop\, power train\, facili
 ty\, software observability\, service model\, and regional infrastructure.
  This talk proposes a five-year engineering roadmap for converting semicon
 ductor innovation into repeatable AI-factory deployment. The central const
 ruct is the validated envelope: a multi-domain operating range in which a 
 chip/package/rack/facility configuration can be manufactured\, powered\, c
 ooled\, serviced\, monitored\, regulated\, and replicated at scale without
  exposing proprietary design details. The lecture will define validated en
 velopes across thermal\, mechanical\, electrical\, fluidic\, manufacturing
 \, serviceability\, telemetry\, safety\, regulatory\, and regional-infrast
 ructure domains\; map key technology drivers (chiplets\, HBM\, optical I/O
 \, power delivery\, liquid cooling\, mechanical reliability\, fleet teleme
 try)\; and propose milestone gates for silicon suppliers\, hyperscalers\, 
 foundry/packaging/OAT ecosystems\, cooling suppliers\, standards bodies\, 
 and policymakers. The roadmap is framed as a decision and validation frame
 work rather than a device forecast and argues that the practical unit of A
 I infrastructure scaling is now the validated chip-to-region stack: valida
 te once\, replicate many times.\n\nSpeaker(s): Gamal Refai-Ahmed\n\nRoom: 
 701A\, Bldg: Taipei Nangang Exhibition Center\, Hall 2 (TaiNEX 2)\, No. 2\
 , Jingmao 2nd Rd.\, Nangang Dist.\, Taipei\, T'ai-pei\, Taiwan
LOCATION:Room: 701A\, Bldg: Taipei Nangang Exhibition Center\, Hall 2 (TaiN
 EX 2)\, No. 2\, Jingmao 2nd Rd.\, Nangang Dist.\, Taipei\, T'ai-pei\, Taiw
 an
ORGANIZER:crkao@ntu.edu.tw
SEQUENCE:88
SUMMARY:IMPACT Distinguished Lecture - From Chip to AI Factory: A Five-Year
  Roadmap for Silicon Suppliers and Hyperscalers
URL;VALUE=URI:https://events.vtools.ieee.org/m/570239
X-ALT-DESC:Description: <br /><p style="text-align: justify\;">Artificial i
 ntelligence (AI) infrastructure is moving from accelerator-level optimizat
 ion toward validated AI-factory capacity. In this regime\, peak silicon pe
 rformance is necessary but insufficient: deployable capacity depends on th
 e coupled behavior of silicon\, heterogeneous package\, substrate\, board\
 , rack\, liquid-cooling loop\, power train\, facility\, software observabi
 lity\, service model\, and regional infrastructure. This talk proposes a f
 ive-year engineering roadmap for converting semiconductor innovation into 
 repeatable AI-factory deployment. The central construct is the&nbsp\;<stro
 ng>validated envelope</strong>: a multi-domain operating range in which a 
 chip/package/rack/facility configuration can be manufactured\, powered\, c
 ooled\, serviced\, monitored\, regulated\, and replicated at scale without
  exposing proprietary design details. The lecture will define validated en
 velopes across thermal\, mechanical\, electrical\, fluidic\, manufacturing
 \, serviceability\, telemetry\, safety\, regulatory\, and regional-infrast
 ructure domains\; map key technology drivers (chiplets\, HBM\, optical I/O
 \, power delivery\, liquid cooling\, mechanical reliability\, fleet teleme
 try)\; and propose milestone gates for silicon suppliers\, hyperscalers\, 
 foundry/packaging/OAT ecosystems\, cooling suppliers\, standards bodies\, 
 and policymakers. The roadmap is framed as a decision and validation frame
 work rather than a device forecast and argues that the practical unit of A
 I infrastructure scaling is now the validated chip-to-region stack: valida
 te once\, replicate many times.</p>
END:VEVENT
END:VCALENDAR