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DTSTART:20260308T030000
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DTSTAMP:20260731T064730Z
UID:D3677E97-A26B-4A3A-8DC7-0E752CCA66F0
DTSTART;TZID=America/New_York:20260915T180000
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DESCRIPTION:At 5 kW and 0.6 V\, an AI processor draws more than 8\,000 A th
 rough its package. No lateral power-delivery network supplies that current
  without spending a large share of the supply voltage on guardband\, and n
 o C4 array carries it without dedicating thousands of bumps to power at th
 e expense of signal escape. The package\, not the transistor\, now sets th
 e limit\, and the resolution is directional: power and heat flow verticall
 y through the substrate while high-bandwidth signal flows horizontally to 
 the perimeter\, so the substrate absorbs the role once played by the print
 ed circuit board. A Perf/W model gives droop scaling linearly with local c
 urrent density while the resulting penalty scales quadratically\, since sw
 itching energy varies with the square of the supply voltage: package-integ
 rated regulation pays twice\, and its advantage grows super-linearly with 
 current density. Embedded regulation collapses the chain from board regula
 tor through PCB and C4 into a vertical path inside the substrate\, cutting
  droop roughly four-fold. In return it demands a build-up substrate reconc
 iling signal density\, stiffness\, thermal conduction and embeddability\, 
 and two enabling numbers: inductor current density rising from 3 toward 6
 –10 A/mm²\, and a higher intermediate bus voltage to hold input current
  down.\n\nSpeaker(s): Francesco Carobolante\, \n\nAgenda: \n06:00 PM - 06:
 30 PM: Networking. Refreshments served.\n\n06:30 PM - 06:35 PM - Introduct
 ion of the speaker\n\n06: 35 PM - 07: 15 PM - Talk and Q &A\n\nRoom: Bluem
 ont Room\, Bldg: Arlington Central Library\, 1015 N Quincy St\, Arlington\
 , Virginia\, United States\, Virtual: https://events.vtools.ieee.org/m/570
 418
LOCATION:Room: Bluemont Room\, Bldg: Arlington Central Library\, 1015 N Qui
 ncy St\, Arlington\, Virginia\, United States\, Virtual: https://events.vt
 ools.ieee.org/m/570418
ORGANIZER:murtyp@ieee.org
SEQUENCE:26
SUMMARY:Local IEEE Meeting: Architecting the Package for a 5 kW AI Processo
 r - Why power delivery\, not the transistor\, now sets the ceiling
URL;VALUE=URI:https://events.vtools.ieee.org/m/570418
X-ALT-DESC:Description: <br /><p class="MsoNormal">At 5 kW and 0.6 V\, an A
 I processor draws more than 8\,000 A through its package. No lateral power
 -delivery network supplies that current without spending a large share of 
 the supply voltage on guardband\, and no C4 array carries it without dedic
 ating thousands of bumps to power at the expense of signal escape. The pac
 kage\, not the transistor\, now sets the limit\, and the resolution is dir
 ectional: power and heat flow vertically through the substrate while high-
 bandwidth signal flows horizontally to the perimeter\, so the substrate ab
 sorbs the role once played by the printed circuit board. A Perf/W model gi
 ves droop scaling linearly with local current density while the resulting 
 penalty scales quadratically\, since switching energy varies with the squa
 re of the supply voltage: package-integrated regulation pays twice\, and i
 ts advantage grows super-linearly with current density. Embedded regulatio
 n collapses the chain from board regulator through PCB and C4 into a verti
 cal path inside the substrate\, cutting droop roughly four-fold. In return
  it demands a build-up substrate reconciling signal density\, stiffness\, 
 thermal conduction and embeddability\, and two enabling numbers: inductor 
 current density rising from 3 toward 6&ndash\;10 A/mm&sup2\;\, and a highe
 r intermediate bus voltage to hold input current down.</p><br /><br />Agen
 da: <br /><p>06:00 PM - 06:30 PM: Networking. Refreshments served.</p>\n<p
 >06:30 PM - 06:35 PM - Introduction of the speaker&nbsp\;</p>\n<p>06: 35 P
 M - 07: 15 PM - Talk and Q &amp\;A</p>
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