BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Africa/Nairobi
BEGIN:STANDARD
DTSTART:19420801T001500
TZOFFSETFROM:+0245
TZOFFSETTO:+0300
TZNAME:EAT
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260808T144826Z
UID:3339CE3A-EBF6-4652-B26C-07A4FA2D9220
DTSTART;TZID=Africa/Nairobi:20260806T200000
DTEND;TZID=Africa/Nairobi:20260806T220000
DESCRIPTION:[]\n\nThis session will be a continuation of our hands-on PCB d
 esign series\, building upon the foundational concepts and layout techniqu
 es covered in earlier sessions.\n\nIn this session\, we will focus on:\n\n
 -\nAdvanced Layout &amp; Routing: Refining trace routing\, managing signal int
 egrity\, and optimizing component placement.\n\n-\nPower &amp; Ground Manageme
 nt: Implementing effective power/ground planes and addressing thermal cons
 iderations.\n\n-\nDesign Rule Verification: Running Design Rule Checks (DR
 C) to ensure accuracy and error-free layouts.\n\n-\nManufacturing Output: 
 Generating essential fabrication and assembly files (Gerber files\, Bill o
 f Materials\, and NC Drill data) required for production.\n\nWhether you&#39;r
 e finalizing your layout or preparing your design for manufacturing\, this
  session will provide practical insights to help move your project from sc
 hematic to completed hardware.\n\nSpeaker(s): Bornface \, \n\nVirtual: htt
 ps://events.vtools.ieee.org/m/571243
LOCATION:Virtual: https://events.vtools.ieee.org/m/571243
ORGANIZER:ieeesightmmu@gmail.com
SEQUENCE:41
SUMMARY:PCB DESIGN SESSION 5
URL;VALUE=URI:https://events.vtools.ieee.org/m/571243
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;img src=&quot;https://events.vtools.ieee.org/v
 tools_ui/media/display/9221d005-61a7-4437-a9ee-8a6a949cb9a1&quot; alt=&quot;&quot; width=
 &quot;409&quot; height=&quot;409&quot;&gt;&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p data-path-to-n
 ode=&quot;2&quot;&gt;&lt;strong data-path-to-node=&quot;2&quot; data-index-in-node=&quot;0&quot;&gt;This session 
 will be a continuation&lt;/strong&gt; of our hands-on PCB design series\, buildi
 ng upon the foundational concepts and layout techniques covered in earlier
  sessions.&lt;/p&gt;\n&lt;p data-path-to-node=&quot;3&quot;&gt;In this session\, we will focus o
 n:&lt;/p&gt;\n&lt;ul data-path-to-node=&quot;4&quot;&gt;\n&lt;li&gt;\n&lt;p data-path-to-node=&quot;4\,0\,0&quot;&gt;&lt;
 strong data-path-to-node=&quot;4\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;Advanced Layout 
 &amp;amp\; Routing:&lt;/strong&gt; Refining trace routing\, managing signal integrit
 y\, and optimizing component placement.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li&gt;\n&lt;p data-path-to-
 node=&quot;4\,1\,0&quot;&gt;&lt;strong data-path-to-node=&quot;4\,1\,0&quot; data-index-in-node=&quot;0&quot;&gt;
 Power &amp;amp\; Ground Management:&lt;/strong&gt; Implementing effective power/grou
 nd planes and addressing thermal considerations.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li&gt;\n&lt;p data
 -path-to-node=&quot;4\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;4\,2\,0&quot; data-index-in-
 node=&quot;0&quot;&gt;Design Rule Verification:&lt;/strong&gt; Running Design Rule Checks (DR
 C) to ensure accuracy and error-free layouts.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li&gt;\n&lt;p data-pa
 th-to-node=&quot;4\,3\,0&quot;&gt;&lt;strong data-path-to-node=&quot;4\,3\,0&quot; data-index-in-nod
 e=&quot;0&quot;&gt;Manufacturing Output:&lt;/strong&gt; Generating essential fabrication and 
 assembly files (Gerber files\, Bill of Materials\, and NC Drill data) requ
 ired for production.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p data-path-to-node=&quot;5&quot;&gt;Whether y
 ou&#39;re finalizing your layout or preparing your design for manufacturing\, 
 this session will provide practical insights to help move your project fro
 m schematic to completed hardware.&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;
END:VEVENT
END:VCALENDAR