BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260831T213908Z UID:E2FB0C83-EB28-44D7-B56E-2CFCFB235DA8 DTSTART;TZID=America/Los_Angeles:20260901T160000 DTEND;TZID=America/Los_Angeles:20260901T180000 DESCRIPTION:The transition from monolithic systems to chiplet-based heterog eneous integration is redefining the design of high-speed interconnects. T his talk presents an overview of the key challenges associated with bandwi dth scaling\, signal integrity\, power delivery\, thermal management\, and interconnect reliability in advanced packaging. It further discusses the impact of interconnect scaling\, surface roughness\, and emerging material s\, including copper–graphene hybrid structures\, on next-generation sys tems. Finally\, the talk emphasizes the importance of electrical–thermal –mechanical co-design and multiphysics optimization in enabling future A I\, HPC\, and data-centric computing architectures. The schedule is as fol lows:\n\n4-4.30 pm - Networking\n\n4.30-6 pm - Lecture\n\nSpeaker(s): Rohi t Sharma\n\nAgenda: \n4-4.30 pm - Networking\n\n4.30-6 pm - Lecture\n\nBld g: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\, Californi a\, United States\, 92121 LOCATION:Bldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\ , California\, United States\, 92121 ORGANIZER:vaishnav.srinivas@gmail.com SEQUENCE:26 SUMMARY:IEEE Lecture - The Future of High-Speed Interconnects: Challenges a nd Opportunities in Heterogeneous Integration URL;VALUE=URI:https://events.vtools.ieee.org/m/573409 X-ALT-DESC:Description: <br /><p style="text-align: justify\;">The transiti on from monolithic systems to chiplet-based heterogeneous integration is r edefining the design of high-speed interconnects. This talk presents an ov erview of the key challenges associated with bandwidth scaling\, signal in tegrity\, power delivery\, thermal management\, and interconnect reliabili ty in advanced packaging. It further discusses the impact of interconnect scaling\, surface roughness\, and emerging materials\, including copper&nd ash\;graphene hybrid structures\, on next-generation systems. Finally\, th e talk emphasizes the importance of electrical&ndash\;thermal&ndash\;mecha nical co-design and multiphysics optimization in enabling future AI\, HPC\ , and data-centric computing architectures. The schedule is as follows:&nb sp\;</p>\n<p>4-4.30 pm - Networking</p>\n<p>4.30-6 pm - Lecture</p><br />< br />Agenda: <br /><p>4-4.30 pm - Networking</p>\n<p>4.30-6 pm - Lecture</ p> END:VEVENT END:VCALENDAR