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DTSTART:20260329T030000
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BEGIN:VEVENT
DTSTAMP:20260827T154215Z
UID:717BB0C1-6195-4088-B5F2-8E34421DDBA0
DTSTART;TZID=Europe/Rome:20260911T090000
DTEND;TZID=Europe/Rome:20260911T163000
DESCRIPTION:We are pleased to invite you to our upcoming IEEE EDS/SSCS/CASS
  Mini-Colloquium on Advanced Semiconductor Technologies and Circuit Design
 \, taking place on September 11.\n\nThis event brings together leading exp
 erts from industry and academia to explore pivotal developments in energy-
 efficient computing\, wide bandgap (WBG) devices\, compact modeling\, and 
 biomedical interfaces. The day will begin with a special tribute to Michae
 l S. Shur honoring his lasting contributions to the field.\n\nAgenda: \nEv
 ent Schedule\n\nTime	Session / Talk Title	Speaker &amp; Affiliation\n09:00 –
  09:05	Welcome &amp; Opening Remarks	Organizers\n09:05 – 09:15	Tribute to Mi
 chael S. Shur	Special Session\n09:15 – 10:05	Leveraging semiconductor te
 chnology for the benefit of society	Fernando Guarin (Director of IEEE Divi
 sion I)\n10:05 – 10:55	Power efficient WBG devices for the green transit
 ion	Mikael Ostling (KTH\, SE)\n10:55 – 11:25	Coffee Break &amp; Networking	
 —\n11:25 – 12:15	Holistic solutions to future computing - not only sca
 ling	Francesca Iacopi (Purdue University\, US)\n12:15 – 13:05	Status of 
 the Compact modeling and its Verilog-A standardization	Wladek Grabinski (M
 OS-AK\, CH &amp; IHP OpenPDK\, DE)\n13:05 – 14:25	Lunch Break	—\n14:25 –
  15:15	Graphene thin film technology for neural interfaces	José Antonio G
 arrido (ICN2\, Spain)\n15:15 – 16:05	Energy-Efficient Analog IC Design: 
 Exploring Solutions at Device\, Circuit and System Levels	Antonio López (
 Public University of Navarra\, Spain)\n\nBldg: Sa Riera\, C/ de Miquel del
 s Sants Oliver\, 2\, Palma\, Baleares\, Spain\, 07122
LOCATION:Bldg: Sa Riera\, C/ de Miquel dels Sants Oliver\, 2\, Palma\, Bale
 ares\, Spain\, 07122
ORGANIZER:francesc.moll@upc.edu
SEQUENCE:4
SUMMARY:IEEE EDS/SSCS/CASS Mini-Colloquium on Advanced Semiconductor Techno
 logies and Circuit Design
URL;VALUE=URI:https://events.vtools.ieee.org/m/574475
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-path-to-node=&quot;2&quot;&gt;We are pleased to in
 vite you to our upcoming IEEE EDS/SSCS/CASS &lt;strong data-path-to-node=&quot;2&quot; 
 data-index-in-node=&quot;45&quot;&gt;Mini-Colloquium on Advanced Semiconductor Technolo
 gies and Circuit Design&lt;/strong&gt;\, taking place on &lt;strong data-path-to-no
 de=&quot;2&quot; data-index-in-node=&quot;136&quot;&gt;September 11&lt;/strong&gt;.&lt;/p&gt;\n&lt;p data-path-t
 o-node=&quot;3&quot;&gt;This event brings together leading experts from industry and ac
 ademia to explore pivotal developments in energy-efficient computing\, wid
 e bandgap (WBG) devices\, compact modeling\, and biomedical interfaces. Th
 e day will begin with a special tribute to &lt;strong data-path-to-node=&quot;3&quot; d
 ata-index-in-node=&quot;251&quot;&gt;Michael S. Shur&lt;/strong&gt; honoring his lasting cont
 ributions to the field.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;h3 data-path-to-node
 =&quot;5&quot;&gt;&lt;strong data-path-to-node=&quot;5&quot; data-index-in-node=&quot;0&quot;&gt;Event Schedule&lt;/
 strong&gt;&lt;/h3&gt;\n&lt;table data-path-to-node=&quot;6&quot;&gt;\n&lt;thead&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;strong&gt;Ti
 me&lt;/strong&gt;&lt;/td&gt;\n&lt;td&gt;&lt;strong&gt;Session / Talk Title&lt;/strong&gt;&lt;/td&gt;\n&lt;td&gt;&lt;str
 ong&gt;Speaker &amp;amp\; Affiliation&lt;/strong&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/thead&gt;\n&lt;tbody&gt;\n&lt;t
 r&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,1\,0\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\
 ,1\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;09:00 &amp;ndash\; 09:05&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;
 \n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,1\,1\,0&quot;&gt;Welcome &amp;amp\; Opening Remarks&lt;
 /span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,1\,2\,0&quot;&gt;Organizers&lt;/span&gt;&lt;/t
 d&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,2\,0\,0&quot;&gt;&lt;strong data-pat
 h-to-node=&quot;6\,2\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;09:05 &amp;ndash\; 09:15&lt;/strong
 &gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,2\,1\,0&quot;&gt;Tribute to Michael
  S. Shur&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,2\,2\,0&quot;&gt;Special Ses
 sion&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,3\,0\,0&quot;&gt;&lt;s
 trong data-path-to-node=&quot;6\,3\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;09:15 &amp;ndash\;
  10:05&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,3\,1\,0&quot;&gt;Leve
 raging semiconductor technology for the benefit of society&lt;/span&gt;&lt;/td&gt;\n&lt;t
 d&gt;&lt;span data-path-to-node=&quot;6\,3\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,3\,2\
 ,0&quot; data-index-in-node=&quot;0&quot;&gt;Fernando Guarin&lt;/strong&gt; (Director of IEEE Divi
 sion I)&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,4\,0\,0&quot;
 &gt;&lt;strong data-path-to-node=&quot;6\,4\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;10:05 &amp;ndas
 h\; 10:55&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,4\,1\,0&quot;&gt;P
 ower efficient WBG devices for the green transition&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span
  data-path-to-node=&quot;6\,4\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,4\,2\,0&quot; dat
 a-index-in-node=&quot;0&quot;&gt;Mikael Ostling&lt;/strong&gt; (KTH\, SE)&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\
 n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,5\,0\,0&quot;&gt;&lt;strong data-path-to-node=
 &quot;6\,5\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;10:55 &amp;ndash\; 11:25&lt;/strong&gt;&lt;/span&gt;&lt;/
 td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,5\,1\,0&quot;&gt;&lt;em data-path-to-node=&quot;6\,5\
 ,1\,0&quot; data-index-in-node=&quot;0&quot;&gt;Coffee Break &amp;amp\; Networking&lt;/em&gt;&lt;/span&gt;&lt;/
 td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,5\,2\,0&quot;&gt;&amp;mdash\;&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\
 n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,6\,0\,0&quot;&gt;&lt;strong data-path-to-node=
 &quot;6\,6\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;11:25 &amp;ndash\; 12:15&lt;/strong&gt;&lt;/span&gt;&lt;/
 td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,6\,1\,0&quot;&gt;Holistic solutions to future
  computing - not only scaling&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\
 ,6\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,6\,2\,0&quot; data-index-in-node=&quot;0&quot;&gt;Fr
 ancesca Iacopi&lt;/strong&gt; (Purdue University\, US)&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\
 n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,7\,0\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,7\
 ,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;12:15 &amp;ndash\; 13:05&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;
 td&gt;&lt;span data-path-to-node=&quot;6\,7\,1\,0&quot;&gt;Status of the Compact modeling and
  its Verilog-A standardization&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6
 \,7\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,7\,2\,0&quot; data-index-in-node=&quot;0&quot;&gt;W
 ladek Grabinski&lt;/strong&gt; (MOS-AK\, CH &amp;amp\; IHP OpenPDK\, DE)&lt;/span&gt;&lt;/td&gt;
 \n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,8\,0\,0&quot;&gt;&lt;strong data-path-
 to-node=&quot;6\,8\,0\,0&quot; data-index-in-node=&quot;0&quot;&gt;13:05 &amp;ndash\; 14:25&lt;/strong&gt;&lt;
 /span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,8\,1\,0&quot;&gt;&lt;em data-path-to-nod
 e=&quot;6\,8\,1\,0&quot; data-index-in-node=&quot;0&quot;&gt;Lunch Break&lt;/em&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;s
 pan data-path-to-node=&quot;6\,8\,2\,0&quot;&gt;&amp;mdash\;&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;
 &lt;span data-path-to-node=&quot;6\,9\,0\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,9\,0\,0
 &quot; data-index-in-node=&quot;0&quot;&gt;14:25 &amp;ndash\; 15:15&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;s
 pan data-path-to-node=&quot;6\,9\,1\,0&quot;&gt;Graphene thin film technology for neura
 l interfaces&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data-path-to-node=&quot;6\,9\,2\,0&quot;&gt;&lt;strong
  data-path-to-node=&quot;6\,9\,2\,0&quot; data-index-in-node=&quot;0&quot;&gt;Jos&amp;eacute\; Antoni
 o Garrido&lt;/strong&gt; (ICN2\, Spain)&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;span data
 -path-to-node=&quot;6\,10\,0\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,10\,0\,0&quot; data-i
 ndex-in-node=&quot;0&quot;&gt;15:15 &amp;ndash\; 16:05&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data
 -path-to-node=&quot;6\,10\,1\,0&quot;&gt;Energy-Efficient Analog IC Design: Exploring S
 olutions at Device\, Circuit and System Levels&lt;/span&gt;&lt;/td&gt;\n&lt;td&gt;&lt;span data
 -path-to-node=&quot;6\,10\,2\,0&quot;&gt;&lt;strong data-path-to-node=&quot;6\,10\,2\,0&quot; data-i
 ndex-in-node=&quot;0&quot;&gt;Antonio L&amp;oacute\;pez&lt;/strong&gt; (Public University of Nava
 rra\, Spain)&lt;/span&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;
END:VEVENT
END:VCALENDAR