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DTSTAMP:20260902T020249Z
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DTSTART;TZID=America/Denver:20261008T190000
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DESCRIPTION:Abstract: As semiconductor manufacturing pushes against the lim
 its of traditional monolithic chip design\, chiplet-based architectures ha
 ve emerged as a transformative solution for the industry. By breaking comp
 lex processors into smaller\, discrete dies\, manufacturers can significan
 tly improve yields\, reduce waste\, and circumvent the hard reticle-size l
 imitations imposed by modern lithography machines. This approach also unlo
 cks powerful cost and efficiency advantages\, allowing engineers to optimi
 ze each functional block by selecting the most appropriate manufacturing n
 ode\, for example\, pairing cutting-edge processes for high-performance lo
 gic with more cost-effective nodes for memory and I/O components.\n\nChipl
 et architectures\, however\, have brought renewed focus to the packaging t
 hat sits between the silicon die and the system PCB. These packages have h
 ad to increase in complexity to support many more chiplet-to-chiplet conne
 ctions. Today’s advanced packages make it possible to combine specialize
 d CPU\, AI\, and graphics modules within a single package. The ability to 
 reuse proven chiplet designs and selectively upgrade individual functional
  blocks without redesigning an entire system represents a shift in how the
  semiconductor industry approaches processor development.\n\nThis talk wil
 l explore how chiplet technology is overcoming the manufacturing\, economi
 c\, and design challenges facing the industry and shaping the future of ad
 vanced semiconductor packaging.\n\nParking: Parking information at CU Boul
 der will be provided to event registrants closer to the event date.\n\n** 
 The Front Range Speaker Series brings together students\, faculty\, IEEE m
 embers\, and engineering professionals for technical talks from experts ac
 ross industry and academia. This event is part of the ongoing speaker seri
 es co-hosted by the IEEE University of Colorado Boulder Student Branch and
  the IEEE Denver Section. This series is open to all levels from technical
  beginners to experts.\n\nUpcoming Talks:\n\n- Thursday\, November 5\, 202
 6:&quot;Package and PCB Materials&quot; by Darren Hitchcock (Panasonic)\n- Thursday\
 , December 3\, 2026: Student presentations showcasing research and industr
 y topics\n\nAgenda: \nExample Agenda\n\n- 6:45–7:00 PM — Arrival and a
 ttendee check-in\n- 7:00–7:10 PM — Welcome and speaker introduction\n-
  7:10–8:10 PM — Speaker presentation\n- 8:10–8:20 PM — Q&amp;A and dis
 cussion\n- 8:20–8:30 PM — Closing remarks and upcoming speaker-series 
 announcements\n\nRoom: ECCR 200\, Bldg: Engineering Center\, 1111 Engineer
 ing Drive\, Boulder\, Colorado\, United States\, 80309
LOCATION:Room: ECCR 200\, Bldg: Engineering Center\, 1111 Engineering Drive
 \, Boulder\, Colorado\, United States\, 80309
ORGANIZER:Tim.swettlen@colorado.edu
SEQUENCE:1334
SUMMARY:Dine &amp; Learn at CU Boulder: Chiplets — What / Why / Where by Judd
  Gerber (Intel Corporation)
URL;VALUE=URI:https://events.vtools.ieee.org/m/575064
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;600&quot; data-end=&quot;641&quot;&gt;&lt;strong da
 ta-start=&quot;600&quot; data-end=&quot;613&quot;&gt;Abstract: &lt;/strong&gt;&lt;span data-olk-copy-sourc
 e=&quot;MessageBody&quot;&gt;As semiconductor manufacturing pushes against the limits o
 f traditional monolithic chip design\, chiplet-based architectures have em
 erged as a transformative solution for the industry. By breaking complex p
 rocessors into smaller\, discrete dies\, manufacturers can significantly i
 mprove yields\, reduce waste\, and circumvent the hard reticle-size limita
 tions imposed by modern lithography machines. This approach also unlocks p
 owerful cost and efficiency advantages\, allowing engineers to optimize ea
 ch functional block by selecting the most appropriate manufacturing node\,
  for example\, pairing cutting-edge processes for high-performance logic w
 ith more cost-effective nodes for memory and I/O components.&lt;/span&gt;&lt;/p&gt;\n&lt;
 p class=&quot;x_MsoNormal&quot;&gt;Chiplet architectures\, however\, have brought renew
 ed focus to the packaging that sits between the silicon die and the system
  PCB. These packages have had to increase in complexity to support many mo
 re chiplet-to-chiplet connections. Today&amp;rsquo\;s advanced packages make i
 t possible to combine specialized CPU\, AI\, and graphics modules within a
  single package. The ability to reuse proven chiplet designs and selective
 ly upgrade individual functional blocks without redesigning an entire syst
 em represents a shift in how the semiconductor industry approaches process
 or development.&lt;/p&gt;\n&lt;p class=&quot;x_MsoNormal&quot;&gt;This talk will explore how chi
 plet technology is overcoming the manufacturing\, economic\, and design ch
 allenges facing the industry and shaping the future of advanced semiconduc
 tor packaging.&lt;/p&gt;\n&lt;p data-start=&quot;646&quot; data-end=&quot;780&quot;&gt;&lt;strong data-start=
 &quot;237&quot; data-end=&quot;249&quot;&gt;Parking:&lt;/strong&gt; Parking information at CU Boulder w
 ill be provided to event registrants closer to the event date.&lt;/p&gt;\n&lt;p dat
 a-start=&quot;646&quot; data-end=&quot;780&quot;&gt;&lt;em&gt;** The Front Range Speaker Series brings 
 together students\, faculty\, IEEE members\, and engineering professionals
  for technical talks from experts across industry and academia. This event
  is part of the ongoing speaker series co-hosted by the IEEE University of
  Colorado Boulder Student Branch and the IEEE Denver Section.&amp;nbsp\;&lt;stron
 g&gt;This series is open to all levels from technical beginners to experts.&lt;/
 strong&gt;&lt;/em&gt;&lt;/p&gt;\n&lt;p data-start=&quot;646&quot; data-end=&quot;780&quot;&gt;&lt;em&gt;&lt;strong&gt;Upcoming 
 Talks:&lt;/strong&gt;&lt;/em&gt;&lt;/p&gt;\n&lt;ul&gt;\n&lt;li data-start=&quot;646&quot; data-end=&quot;780&quot;&gt;&lt;em&gt;Th
 ursday\, November 5\, 2026:&quot;Package and PCB Materials&quot; by Darren Hitchcock
  (Panasonic)&lt;/em&gt;&lt;/li&gt;\n&lt;li data-start=&quot;646&quot; data-end=&quot;780&quot;&gt;&lt;em&gt;Thursday\,
  December 3\, 2026: Student presentations showcasing research and industry
  topics&lt;/em&gt;&lt;/li&gt;\n&lt;/ul&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p class=&quot;PDq2pG_selecti
 onAnchorContainer&quot; data-start=&quot;63&quot; data-end=&quot;81&quot;&gt;&lt;strong data-start=&quot;63&quot; d
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 7&quot;&gt;\n&lt;li data-start=&quot;82&quot; data-end=&quot;132&quot;&gt;&lt;strong data-start=&quot;84&quot; data-end=&quot;
 100&quot;&gt;6:45&amp;ndash\;7:00 PM&lt;/strong&gt; &amp;mdash\; Arrival and attendee check-in&lt;/
 li&gt;\n&lt;li data-start=&quot;133&quot; data-end=&quot;186&quot;&gt;&lt;strong data-start=&quot;135&quot; data-end
 =&quot;151&quot;&gt;7:00&amp;ndash\;7:10 PM&lt;/strong&gt; &amp;mdash\; Welcome and speaker introduct
 ion&lt;/li&gt;\n&lt;li data-start=&quot;187&quot; data-end=&quot;228&quot;&gt;&lt;strong data-start=&quot;189&quot; dat
 a-end=&quot;205&quot;&gt;7:10&amp;ndash\;8:10 PM&lt;/strong&gt; &amp;mdash\; Speaker presentation&lt;/li
 &gt;\n&lt;li data-start=&quot;229&quot; data-end=&quot;268&quot;&gt;&lt;strong data-start=&quot;231&quot; data-end=&quot;
 247&quot;&gt;8:10&amp;ndash\;8:20 PM&lt;/strong&gt; &amp;mdash\; Q&amp;amp\;A and discussion&lt;/li&gt;\n&lt;
 li data-start=&quot;269&quot; data-end=&quot;347&quot;&gt;&lt;strong data-start=&quot;271&quot; data-end=&quot;287&quot;
 &gt;8:20&amp;ndash\;8:30 PM&lt;/strong&gt; &amp;mdash\; Closing remarks and upcoming speake
 r-series announcements&lt;/li&gt;\n&lt;/ul&gt;
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