BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
DTSTART:20260308T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20261101T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260904T153154Z
UID:83C4EA85-1C5A-4CF7-B60B-562C2FC15782
DTSTART;TZID=America/Los_Angeles:20261023T090000
DTEND;TZID=America/Los_Angeles:20261023T133000
DESCRIPTION:[]This no-cost workshop brings together five industry experts (
 plus an optional lab tour) to discuss the latest 2.5D/3D/3.5D semiconducto
 r packaging solutions for HPC and AI. It highlights the growing challenges
  of fault isolation (FI) and failure analysis (FA) in dense interconnects 
 such as hybrid bonding and micro bump arrays\, reviews new thermal managem
 ent options (metallic TIMs\, low-temp solders)\, showcases advanced non-de
 structive inspection tools (computed laminography and high resolution CT)\
 , and introduces cutting edge microscopy techniques (SAM and PiFM) for def
 ect characterization\, while outlining emerging FI-FA workflows and tool r
 oadmaps for reliable\, scalable AI and data center hardware. Attendees wil
 l gain insight into current industry troubleshooting workflows and a forwa
 rd-looking roadmap of the tools and techniques being developed to address 
 advanced packaging failures. Additionally\, the optional lab tour can help
  the attendees understand the tools and techniques discussed in the lectur
 es.\n\nFour guided training talks with small-group interaction:\n9:00: Adv
 anced Packaging for AI – Challenges and Roadmaps in Fault Isolation and 
 Failure Analysis\n9:30: Metal TIM and Low-Temp Solder Paste for HPC and AI
  Industry Challenges\n10:00: Failure Analysis of Electronic Components for
  AI and Data Center Infrastructure\n10:30:  High-Resolution 3D X-Ray Inspe
 ction for Advanced Packaging Integration\n11:00: Scanning Acoustic Microsc
 opy (SAM) and Photo-induced Force Microscopy (PiFM) for Defect Identificat
 ion and Characterization in AI Hardware\n\n11:30: lunch\, social/networkin
 g\, and optional lab tours\n\nSpeaker(s): Yan Li\, David Hu\, Audrey Chamo
 ire \, Jeff Gelb\, Austin Barnes\n\nCovalent Corp.\, 925 Thompson Place\, 
 Sunnyvale\, California\, United States\, 94085\, Virtual: https://events.v
 tools.ieee.org/m/575155
LOCATION:Covalent Corp.\, 925 Thompson Place\, Sunnyvale\, California\, Uni
 ted States\, 94085\, Virtual: https://events.vtools.ieee.org/m/575155
ORGANIZER:p.wesling@ieee.org
SEQUENCE:36
SUMMARY:Workshop: Decoding AI Hardware - Materials\, Metrology\, and Failur
 e Analysis in Advanced Packaging
URL;VALUE=URI:https://events.vtools.ieee.org/m/575155
X-ALT-DESC:Description: <br /><p><img style="float: right\;" src="https://e
 vents.vtools.ieee.org/vtools_ui/media/display/94618c62-d17c-4005-9e74-d4e4
 aa5cb75c" alt="" width="500" height="250">This no-cost workshop brings tog
 ether five industry experts (plus an optional lab tour) to discuss the lat
 est 2.5D/3D/3.5D semiconductor packaging solutions for HPC and AI. It high
 lights the growing challenges of fault isolation (FI) and failure analysis
  (FA) in dense interconnects such as hybrid bonding and micro bump arrays\
 , reviews new thermal management options (metallic TIMs\, low-temp solders
 )\, showcases advanced non-destructive inspection tools (computed laminogr
 aphy and high resolution CT)\, and introduces cutting edge microscopy tech
 niques (SAM and PiFM) for defect characterization\, while outlining emergi
 ng FI-FA workflows and tool roadmaps for reliable\, scalable AI and data c
 enter hardware. Attendees will gain insight into current industry troubles
 hooting workflows and a forward-looking roadmap of the tools and technique
 s being developed to address advanced packaging failures. Additionally\, t
 he optional lab tour can help the attendees understand the tools and techn
 iques discussed in the lectures.&nbsp\;</p>\n<p>Four guided training talks
  with small-group interaction:<br>9:00: <strong>Advanced Packaging for AI<
 /strong> &ndash\; Challenges and Roadmaps in Fault Isolation and Failure A
 nalysis<br>9:30: <strong>Metal TIM and Low-Temp Solder Paste</strong> for 
 HPC and AI Industry Challenges<br>10:00:&nbsp\;<strong>Failure Analysis of
  Electronic Components</strong> for AI and Data Center Infrastructure<br>1
 0:30:<strong>&nbsp\;</strong><strong> High-Resolution 3D X-Ray Inspection 
 </strong>for Advanced Packaging Integration<br>11:00: <strong>Scanning Aco
 ustic Microscopy (SAM)</strong> and Photo-induced Force Microscopy (PiFM) 
 for Defect Identification and Characterization in AI Hardware</p>\n<p>11:3
 0: lunch\, social/networking\, and optional lab tours</p>
END:VEVENT
END:VCALENDAR