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PRODID:IEEE vTools.Events//EN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
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BEGIN:VEVENT
DTSTAMP:20260901T054118Z
UID:1352A9CD-FED7-4F20-AD25-21247643684B
DTSTART;TZID=Asia/Kolkata:20260910T110000
DTEND;TZID=Asia/Kolkata:20260910T120000
DESCRIPTION:Electrostatic Discharge (ESD) has been a constant reliability c
 oncern for IC technologies for several decades\, and it is becoming a road
 block to newer applications for electronic devices. The seminar will begin
  with the fundamentals of the ESD threat and how this led to the developme
 nt of protection designs at the IC level and at the system level. These IC
 -level protection circuits face different challenges for Digital\, Analog\
 , and RF circuits. While on-chip protection design is important for the IC
  package devices\, external ESD events have to be addressed at the system 
 interfaces such as USB and HDMI ports. The seminar will present a review o
 f these different design strategies and address the problems posed by adva
 nced technologies while meeting ultra-IO high-speed performance requiremen
 ts. The talk will conclude with a survey of the upcoming challenges from e
 merging technologies such as GaN and CNT\, as well as IoT applications. So
 me of the critical issues of electrical overstress (EOS) during automotive
  applications will also be reviewed. Finally\, the talk will touch upon th
 e new ventures into machine learning and AI for ESD applications.\n\nSpeak
 er(s): \, Dr. Charvaka Duvvury\n\nRoom: 214\, Bldg: ACES Building\, IIT KA
 NPUR\, IIT Kanpur\, Kanpur\, Uttar Pradesh\, India\, 208016
LOCATION:Room: 214\, Bldg: ACES Building\, IIT KANPUR\, IIT Kanpur\, Kanpur
 \, Uttar Pradesh\, India\, 208016
ORGANIZER:avinashlahgere@gmail.com
SEQUENCE:17
SUMMARY:IEEE EDS Mini-Colloquium: IEEE EDS Distinguished Lecture by Dr. Cha
 rvaka Duvvury on "ESD Phenomena and Design in Advanced IC Technologies" 
URL;VALUE=URI:https://events.vtools.ieee.org/m/575175
X-ALT-DESC:Description: <br /><p><span style="font-size: 10.0pt\; font-fami
 ly: 'Courier New'\;">Electrostatic Discharge (ESD) has been a constant rel
 iability concern for IC technologies for several decades\, and it is becom
 ing a roadblock to newer applications for electronic devices. The seminar 
 will begin with the fundamentals of the ESD threat and how this led to the
  development of protection designs at the IC level and at the system level
 . These IC-level protection circuits face different challenges for Digital
 \, Analog\, and RF circuits. While on-chip protection design is important 
 for the IC package devices\, external ESD events have to be addressed at t
 he system interfaces such as USB and HDMI ports. The seminar will present 
 a review of these different design strategies and address the problems pos
 ed by advanced technologies while meeting ultra-IO high-speed performance 
 requirements. The talk will conclude with a survey of the upcoming challen
 ges from emerging technologies such as GaN and CNT\, as well as IoT applic
 ations. Some of the critical issues of electrical overstress (EOS) during 
 automotive applications will also be reviewed. Finally\, the talk will tou
 ch upon the new ventures into machine learning and AI for ESD applications
 .</span></p>
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