BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Phoenix BEGIN:STANDARD DTSTART:19671029T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260902T101401Z UID:2C2DD6BC-8FB9-4A46-A1A9-9C2B795212DB DTSTART;TZID=America/Phoenix:20261001T173000 DTEND;TZID=America/Phoenix:20261001T193000 DESCRIPTION:Glass Core Substrates – Advanced Packaging Pivot driving futu re AI and HPC Chip Performance\n\nSrinivas V. Pietambaram\, Senior Princip al Engineer\,\n\nAdvanced Packaging Technology Development (APTD)\, Intel Foundry\, Intel Corporation\n\nAbstract: With ever-increasing demand for m ore powerful compute and the inevitable move of the semiconductor industry into the heterogeneous era that integrates multiple “chiplets” in a p ackage\, significant improvements in signaling speed\, power delivery\, de sign rules and stability of package substrates will be imperative. Scaling of traditional organic core substrates\, which has served reliably over t he last two and a half decades\, is running out of gas due to intrinsic li mitations in dimensional stability\, flatness and through-hole density. Gl ass Core Substrates\, which Intel Foundry’s APTD organization has been r esearching and developing for over a decade\, can allow the continuation o f bump pitch scaling\, design rule scaling and form factor scaling through their superior mechanical properties and large-scale integration of multi ple chiplets in a package due to its tunable modulus\, dimensional stabili ty and a CTE that is closer to that of silicon. It can also enable an inte grated photonic-electronic platform as electrical wiring\, and optical wav eguides can co-exist in the same glass substrate.\n\nIn this talk\, we sho wcase some of the breakthrough technologies and materials innovations Inte l foundry has developed to overcome the critical bottlenecks that have pla gued the commercialization of glass core technology. We also present succe ssful co-formation of both electrical TGVs and Optical waveguides in the s ame glass substrate exhibiting a consistent low loss light transmission ac ross the waveguides created in the glass. These advances are significant a nd paving the path for successful commercialization of this technology and enabling the scalability of the packages to finer design rules\, ultra la rge area die complexes and Hyper Large Form Factor demanded by HPC and AI applications.\n\nBiography: Srinivas (Srini) Pietambaram is a Senior Princ ipal Engineer in Advanced Packaging Technology Development Substrate & Waf er Assembly Organization (APTD:S&WA) of Intel Foundry\, Intel Corporation. He is technical lead responsible for driving disruptive packaging technol ogies and innovations with a recent focus on glass core substrates and co- packaged optics. Srini is the recipient of Intel Inventor of the year in 2 023\, first such recognition awarded at Intel in the field of packaging fo r his breakthrough innovations in substrates and pivotal work in developin g glass core substrates. He has multiple conference presentations\, invite d talks and is a member of the ECTC Interconnects Committee. He received h is Ph.D. in Materials Science & Engineering from University of Florida in 2001 and worked with Motorola Labs for 10 years before joining Intel in 20 11. Outside of work\, Srini likes to spend time and travel with his family and enjoys listening to Indian Carnatic Music. He is also an avid sports fan with a special liking to Cricket and Gator Football.\n\nLocation: Macr o Technology Works Building Conference Room 3654 ([Google Maps](https://ma ps.app.goo.gl/8pmm79TXL5teH3Ux7))\n\nAgenda:\nRefreshments: 5:30-6:00pm\nS eminar Talk: 6:00-7:00pm\nMTW Tour: 7:00-7:30pm\n\nBldg: Macro Technology Works (MTW)\, 7700 S River Pkwy\, Tempe\, Arizona\, United States\, 85284 LOCATION:Bldg: Macro Technology Works (MTW)\, 7700 S River Pkwy\, Tempe\, A rizona\, United States\, 85284 ORGANIZER:lkhwang@asu.edu SEQUENCE:91 SUMMARY:2026 IEEE EPS Phoenix Section Seminar: Glass Core Substrates – Ad vanced Packaging Pivot driving future AI and HPC Chip Performance by Dr. S rinivas V. Pietambaram (Intel) URL;VALUE=URI:https://events.vtools.ieee.org/m/575393 X-ALT-DESC:Description: <br /><h3 class="p1" style="text-align: center\;">G lass Core Substrates &ndash\; Advanced Packaging Pivot driving future AI a nd HPC Chip Performance</h3>\n<p class="p2" style="text-align: center\;">S rinivas V. Pietambaram\, Senior Principal Engineer\,</p>\n<p class="p2" st yle="text-align: center\;">Advanced Packaging Technology Development (APTD )\, Intel Foundry\, Intel Corporation</p>\n<p class="p2"><strong>Abstract: </strong> With ever-increasing demand for more powerful compute and the in evitable move of the semiconductor industry into the heterogeneous era tha t integrates multiple &ldquo\;chiplets&rdquo\; in a package\, significant improvements in signaling speed\, power delivery\, design rules and stabil ity of package substrates will be imperative. Scaling of traditional organ ic core substrates\, which has served reliably over the last two and a hal f decades\, is running out of gas due to intrinsic limitations in dimensio nal stability\,&nbsp\;flatness and through-hole density. Glass Core Substr ates\, which Intel Foundry&rsquo\;s APTD organization has been researching and&nbsp\;developing for over a decade\, can allow the continuation of bu mp pitch scaling\, design rule scaling and form factor scaling through&nbs p\;their superior mechanical properties and large-scale integration of mul tiple chiplets in a package due to its tunable modulus\,&nbsp\;dimensional stability and a CTE that is closer to that of silicon. It can also enable an integrated photonic-electronic platform as&nbsp\;electrical wiring\, a nd optical waveguides can co-exist in the same glass substrate.</p>\n<p cl ass="p2">In this talk\, we showcase some of the breakthrough technologies and materials innovations Intel foundry has developed to&nbsp\;overcome th e critical bottlenecks that have plagued the commercialization of glass co re technology. We also present successful&nbsp\;co-formation of both elect rical TGVs and Optical waveguides in the same glass substrate exhibiting a consistent low loss light&nbsp\;transmission across the waveguides create d in the glass. These advances are significant and paving the path for suc cessful&nbsp\;commercialization of this technology and enabling the scalab ility of the packages to finer design rules\, ultra large area die&nbsp\;c omplexes and Hyper Large Form Factor demanded by HPC and AI applications.< /p>\n<p class="p2"><img src="https://events.vtools.ieee.org/vtools_ui/medi a/display/471334e3-42b2-4cd0-bb2c-1d01b1e1e08e" width="185" height="227">< /p>\n<p class="p2"><strong>Biography: </strong>Srinivas (Srini) Pietambara m is a Senior Principal Engineer in&nbsp\;Advanced Packaging Technology De velopment Substrate &amp\; Wafer&nbsp\;Assembly Organization (APTD:S&amp\; WA) of Intel Foundry\, Intel&nbsp\;Corporation. He is technical lead respo nsible for driving disruptive&nbsp\;packaging technologies and innovations with a recent focus on glass&nbsp\;core substrates and co-packaged optics . Srini is the recipient of Intel&nbsp\;Inventor of the year in 2023\, fir st such recognition awarded at Intel in&nbsp\;the field of packaging for h is breakthrough innovations in substrates&nbsp\;and pivotal work in develo ping glass core substrates. He has multiple&nbsp\;conference presentations \, invited talks and is a member of the ECTC&nbsp\;Interconnects Committee . He received his Ph.D. in Materials Science&nbsp\;&amp\; Engineering from University of Florida in 2001 and worked with&nbsp\;Motorola Labs for 10 years before joining Intel in 2011. Outside of&nbsp\;work\, Srini likes to spend time and travel with his family and enjoys&nbsp\;listening to India n Carnatic Music. He is also an avid sports fan with&nbsp\;a special likin g to Cricket and Gator Football.</p>\n<p><strong>Location:</strong>&nbsp\; Macro Technology Works Building Conference Room 3654 (<a href="https://map s.app.goo.gl/8pmm79TXL5teH3Ux7">Google Maps</a>)</p>\n<p><strong>Agenda:<b r></strong>Refreshments: 5:30-6:00pm<br>Seminar Talk: 6:00-7:00pm<br>MTW T our: 7:00-7:30pm</p> END:VEVENT END:VCALENDAR