BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD DTSTART:19910915T010000 TZOFFSETFROM:+0900 TZOFFSETTO:+0800 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260907T030445Z UID:18C47F95-9BF5-4575-A955-44A57D8065AC DTSTART;TZID=Asia/Shanghai:20260909T100000 DTEND;TZID=Asia/Shanghai:20260909T230000 DESCRIPTION:The relentless demand for multi-gigabit wireless communication and high-resolution sensing drives rapid innovation in D-band (110–170 G Hz) systems. However\, realizing efficient and scalable active phased arra ys at these frequencies remains challenging due to high cost\, interconnec t losses\, packaging parasitics\, and heterogeneous integration constraint s. This talk presents a holistic\, system-level approach to low-loss D-ban d phased array integration that unifies circuit\, antenna\, and packaging co-design. Leveraging both silicon-based (CMOS\, SiGe) and III–V integra ted circuits\, the approach emphasizes optimized beamformer and power ampl ifier architectures combined with low-cost 2D scalable\, wide-angle scanni ng wideband antenna arrays implemented using low-cost PCB processes. Throu gh electromagnetic co-optimization and advanced interconnect engineering\, the framework achieves significant reduction in loss and improvement in o verall system efficiency. Measured D-band results from prototype modules d emonstrate wide-angle beam steering and data transmission rates up to 100 Gb/s. These results confirm the feasibility of steerable\, high-capacity a rrays suitable for both communication and sensing platforms.\n\nCo-sponsor ed by: College of Electronic Science and Engineering\, jilin University\; State Key Laboratory of Integrated Optoelectronics\, JLU Region.\n\nSpeake r(s): Kamil\n\nVirtual: https://events.vtools.ieee.org/m/576210 LOCATION:Virtual: https://events.vtools.ieee.org/m/576210 ORGANIZER:smalld729@hotmail.com SEQUENCE:13 SUMMARY:From Chip to System: A Holistic Approach to 2D Scalable Low-Loss D- Band Active Phased Array Realization URL;VALUE=URI:https://events.vtools.ieee.org/m/576210 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\; text-justify: inter-ideograph\;">The relentless demand for multi-giga bit wireless communication and high-resolution sensing drives rapid innova tion in D-band (110&ndash\;170 GHz) systems. However\, realizing efficient and scalable active phased arrays at these frequencies remains challengin g due to high cost\, interconnect losses\, packaging parasitics\, and hete rogeneous integration constraints. This talk presents a holistic\, system- level approach to low-loss D-band phased array integration that unifies ci rcuit\, antenna\, and packaging co-design. Leveraging both silicon-based ( CMOS\, SiGe) and III&ndash\;V integrated circuits\, the approach emphasize s optimized beamformer and power amplifier architectures combined with low -cost 2D scalable\, wide-angle scanning wideband antenna arrays implemente d using low-cost PCB processes. Through electromagnetic co-optimization an d advanced interconnect engineering\, the framework achieves significant r eduction in loss and improvement in overall system efficiency. Measured D- band results from prototype modules demonstrate wide-angle beam steering a nd data transmission rates up to 100 Gb/s. These results confirm the feasi bility of steerable\, high-capacity arrays suitable for both communication and sensing platforms.</p>\n<p class="MsoNormal" style="text-align: justi fy\; text-justify: inter-ideograph\;">&nbsp\;</p> END:VEVENT END:VCALENDAR