BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Pacific BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260909T182409Z UID:BC7F4C62-E71D-4D1D-9B5F-5C44BB527938 DTSTART;TZID=US/Pacific:20261002T130000 DTEND;TZID=US/Pacific:20261002T140000 DESCRIPTION:IEEE SSCS Oregon Chapter October Meeting and Seminar\n\nJoin us for a talk from SSCS Distinguished Lecturer Prof. Jae-sun Seo from Cornel l Tech on Friday\, October\, 2nd\, 2026. The seminar will be held from 1:0 0pm to 2:00pm (PDT) via a Virtual format. Please register for the meeting link and information.\n\nTopic:\n\nRecent Digital Compute-In-Memory Design s with Various Precision/Sparsity Schemes and SoC-level Evaluation\n\nAbst ract:\n\nThis talk will present the recent landscape of digital compute-in -memory (CIM) designs for AI applications from my research group and the l iterature. It will feature digital CIM macro chip designs with sparse comp uting using compressed weights\, low-to-high precision support\, and diffe rent number formats including integer\, floating-point\, and microscaling. While high energy-efficiencies have been reported at the CIM macro levels \, it is important to evaluate the energy-efficiency of CIM based accelera tors at the system-on-chip (SoC) level for practical system considerations . We present collective benchmarking framework development efforts for 2D SoC and 3D IC designs\, showcasing the benefits and considerations of CIM designs at the system level.\n\nSpeaker Biography:\n\nJae-sun Seo is an As sociate Professor at the ECE department at Cornell Tech since July 2023\, before which he was an Associate/Assistant Professor at Arizona State Univ ersity since 2014. He was a visiting researcher at Meta Reality Labs from 2022 to 2023\, and he worked at IBM T. J. Watson Research Center from 2010 to 2013.\n\nHis research interests include efficient ASIC and FPGA hardwa re design of machine learning algorithms and neuromorphic computing. Dr. S eo was a recipient of the 2012 IBM Outstanding Technical Achievement Award \, 2017 NSF CAREER Award\, 2020 Intel Outstanding Researcher Award\, and 2 022 IEEE TVLSI Best Paper Award. He has served on the technical program co mmittees for ISSCC\, ESSERC\, ISCA\, HPCA\, MLSys\, DAC\, DATE\, etc.\n\nS peaker(s): Prof. Jae-sun Seo\n\nAgenda: \n1:00pm - 2:00pm: Professional/Ca reer Seminar\n\nVirtual: https://events.vtools.ieee.org/m/576764 LOCATION:Virtual: https://events.vtools.ieee.org/m/576764 ORGANIZER:rdorrance@ieee.org SEQUENCE:22 SUMMARY:IEEE SSCS Oregon Chapter October Meeting and Seminar (Virtual) URL;VALUE=URI:https://events.vtools.ieee.org/m/576764 X-ALT-DESC:Description: <br /><p><span style="text-decoration: underline\; color: #000000\;">IEEE SSCS Oregon Chapter October Meeting and Seminar</sp an></p>\n<p><span style="color: #000000\;">Join us for a talk from SSCS Di stinguished Lecturer Prof. Jae-sun Seo from Cornell Tech on Friday\, Octob er\, 2nd\, 2026. The seminar will be held from 1:00pm to 2:00pm (PDT) via a Virtual format. Please register for the meeting link and information.</s pan></p>\n<p>&nbsp\;</p>\n<p><span style="color: #000000\;">Topic:</span>< /p>\n<p>Recent Digital Compute-In-Memory Designs with Various Precision/Sp arsity Schemes and SoC-level Evaluation</p>\n<p>&nbsp\;</p>\n<p><span styl e="color: #000000\;">Abstract:</span></p>\n<p>This talk will present the r ecent landscape of digital compute-in-memory (CIM) designs for AI applicat ions from my research group and the literature. It will feature digital CI M macro chip designs with sparse computing using compressed weights\, low- to-high precision support\, and different number formats including integer \, floating-point\, and microscaling. While high energy-efficiencies have been reported at the CIM macro levels\, it is important to evaluate the en ergy-efficiency of CIM based accelerators at the system-on-chip (SoC) leve l for practical system considerations. We present collective benchmarking framework development efforts for 2D SoC and 3D IC designs\, showcasing th e benefits and considerations of CIM designs at the system level.</p>\n<p> &nbsp\;</p>\n<p><span style="color: #000000\;">Speaker Biography:</span></ p>\n<p>Jae-sun Seo is an Associate Professor at the ECE department at Corn ell Tech since July 2023\, before which he was an Associate/Assistant Prof essor at Arizona State University since 2014. He was a visiting researcher at Meta Reality Labs from 2022 to 2023\, and he worked at IBM T. J. Watso n Research Center from 2010 to 2013.</p>\n<p>His research interests includ e efficient ASIC and FPGA hardware design of machine learning algorithms a nd neuromorphic computing. Dr. Seo was a recipient of the 2012 IBM Outstan ding Technical Achievement Award\, 2017 NSF CAREER Award\, 2020 Intel Outs tanding Researcher Award\, and 2022 IEEE TVLSI Best Paper Award. He has se rved on the technical program committees for ISSCC\, ESSERC\, ISCA\, HPCA\ , MLSys\, DAC\, DATE\, etc.</p><br /><br />Agenda: <br /><p>1:00pm - 2:00p m: Professional/Career Seminar</p> END:VEVENT END:VCALENDAR