BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0600 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260912T170227Z UID:DBA4E3A0-A5E5-4EF1-8DA5-EB63B8245866 DTSTART;TZID=America/Chicago:20261001T080000 DTEND;TZID=America/Chicago:20261002T170000 DESCRIPTION:The workshop On Chip Design and Fabrication is a 2-day intensiv e program that provides the opportunity to design integrated circuits from an idea to manufacture a real chip. This is a hands-on\, beginner-friendl y course\, guiding participants through the world of silicon design.\n\nTh e event will be hosted during the [Latin America and Caribbean Semiconduct or Summit](https://lacss.ieee.org/) from 1-2 October 2026 in Panama City\, Panama. The Summer Lab will be sponsored by the [IEEE Division I Open Sil icon initiative](https://technical-community-spotlight.ieee.org/democratiz ing-microelectronics-ieee-division-i-open-silicon-initiative/)under the IE EE Electron Devices Society EDS\, Circuit and Systems Society CAS\, and So lid-States Circuits Society.\n\nThe event offers up to 40 scholarships aim ed to IEEE professionals or students from Latin America with an advanced l evel of microelectronics. The course will be taught entirely in English by an experienced member of the [Tiny Tapeout](https://tinytapeout.com/)engi neering team\, ensuring expert guidance throughout.\n\nThe goal is to give students hands-on experience with building their own application-specific integrated circuits ASIC and taking them all the way through to productio n - with the goal of holding a fully-packaged and ready-to-use chip in the ir hand at the end of the process. Each student that successfully submits a design that meets all guidelines will receive their chip fabricated.\n\n Short-listed candidates will be asked to pay a $60.00 USD fee to cover inc identals during the course.\nPayment is required to reserve and guarantee your spot after you have been preselected.\n\nParticipants are encouraged to bring their own laptop computer and satisfy with the following technica l skills:\n\n- Advanced English level (fluency required)\n- Microelectroni cs and advanced principles in Semiconductors\n- Knowledge about Transistor s (bipolar and FET)\n- CMOS\n- Linux\n- Scripting language\n- Hardware des cription languages\n\nScholarship includes:\n\n- Complete course in IC des ign\n- A real chip fabrication sponsored by the Open Silicon Initiative an d manufactured by Tiny Tapeout\n- Lodging for 3 nights (double-occupancy r ooms)\n- Meals during the summer school (including breakfast and lunch)\n- Opportunity to attend the LACSS conference and mingle among experts in se miconductors\n- Opportunity to attend the EDS/CASS MQ on Saturday October 3rd.\n- Certification of completion\n\nNot included:\n\n- Travel (each app licant is responsible for travel arrangements)\n- Visa application fees\n- Transportation from and to the airport\n- Dinner or additional meals afte r the sessions\n- Incidentals or medical emergency (participants are encou raged to have a medical insurance)\n\n[]\n\nCo-sponsored by: National Secr etariat for Science\, Technology\, and Innovation (SENACYT) \; Center for Advanced Semiconductor Technologies (C-TASC AIP)\; IEEE Division\, Open Si licon initiative\, IEEE EDS\, IEEE CAS\, InchFab\n\nAgenda: \nDay 1: Thu rsday\, October 1\n\n- 8:30 – 9:30 AM: Event Opening Session (Introducti on)\n- 9:30 – 10:30 AM: Draw a transistor that could be used in a logic gate\n- 10:30 AM – 12:00 PM: Practice\n- 12:00 – 1:00 PM: Lunch\n- 1:0 0 – 2:00 PM: Build a simple digital design using logic gates\n- 2:00 – 3:00 PM: Practice\n- 3:00 – 3:15 PM: Break\n- 3:15 – 4:15 PM: Generat e the ASIC files from your design\n- 4:15 – 5:15 PM: Practice\n\nDay 2: Friday\, October 2\n\n- 9:00 – 10:00 AM: Submit your design to be manufa ctured on the next Tiny Tapeout chip\n- 10:00 AM – 12:00 PM: Practice\n- 12:00 – 1:00 PM: Lunch\n- 1:00 – 4:00 PM: Work on designs & Q&A sessi on with instructor\n\nBldg: Convention Center (184)\, City of Knowledge \, Clayton\, Estanislao Orobio Street \, Panamá\, Panama\, Panama LOCATION:Bldg: Convention Center (184)\, City of Knowledge \, Clayton\, Est anislao Orobio Street \, Panamá\, Panama\, Panama ORGANIZER:ieeecaspanama@gmail.com SEQUENCE:37 SUMMARY:workshop On Chip Design and Fabrication URL;VALUE=URI:https://events.vtools.ieee.org/m/577339 X-ALT-DESC:Description: <br /><div>The w<strong>orkshop On Chip Design and Fabrication</strong> is a 2-day intensive program that provides the opport unity to design integrated circuits from an idea to manufacture a real chi p. This is a hands-on\, beginner-friendly course\, guiding participants th rough the world of silicon design.</div>\n<div>&nbsp\;</div>\n<div>The eve nt will be hosted during the&nbsp\;<a href="https://lacss.ieee.org/">Latin America and Caribbean Semiconductor Summit</a>&nbsp\;from&nbsp\;<strong>1 -2 October 2026 in Panama City\, Panama</strong>. The Summer Lab will be s ponsored by the&nbsp\;<a href="https://technical-community-spotlight.ieee. org/democratizing-microelectronics-ieee-division-i-open-silicon-initiative /">IEEE Division I Open Silicon initiative&nbsp\;</a>under the IEEE Electr on Devices Society EDS\, Circuit and Systems Society CAS\, and Solid-State s Circuits Society.&nbsp\;</div>\n<div>&nbsp\;</div>\n<div>\n<div>The even t offers up to 40 scholarships aimed to IEEE professionals or students fro m Latin America with an advanced level of microelectronics.&nbsp\;<strong> The course will be taught entirely in English by&nbsp\;an experienced memb er of the&nbsp\;<a href="https://tinytapeout.com/">Tiny Tapeout&nbsp\;</a> engineering team\, ensuring expert guidance throughout.&nbsp\;&nbsp\;</str ong></div>\n<div>&nbsp\;</div>\n<div>The goal is to give&nbsp\;students ha nds-on experience with building their own application-specific integrated circuits ASIC and taking them all the way through to production - with the goal of holding a fully-packaged and ready-to-use chip in their hand at t he end of the process.&nbsp\; Each student that successfully submits a des ign that meets all guidelines will receive their chip fabricated.</div>\n< div>&nbsp\;</div>\n<div>\n<div><u><strong><em>Short-listed candidates will be asked to pay a $60.00 USD fee to cover incidentals during the course.& nbsp\;</em></strong></u></div>\n</div>\n<div><strong>Payment is required t o reserve and guarantee your spot after you have been preselected.&nbsp\;< /strong></div>\n<div><strong>&nbsp\;</strong></div>\n<div><em>Participants are encouraged to bring their own laptop computer and satisfy with the fo llowing technical skills:</em></div>\n</div>\n<div>\n<ul>\n<li>Advanced En glish level (fluency required)</li>\n<li>Microelectronics and advanced pri nciples in Semiconductors</li>\n<li>Knowledge about Transistors (bipolar a nd FET)</li>\n<li>CMOS</li>\n<li>Linux</li>\n<li>Scripting language</li>\n <li>Hardware description languages</li>\n</ul>\n<div><strong>Scholarship i ncludes:</strong></div>\n<div>\n<ul>\n<li>Complete course in IC design</li >\n<li>A real chip fabrication sponsored by the Open Silicon Initiative an d manufactured by Tiny Tapeout</li>\n<li>Lodging for 3 nights (double-occu pancy rooms)</li>\n<li>Meals during the summer school (including breakfast and lunch)</li>\n<li>Opportunity to attend the LACSS conference and mingl e among experts in semiconductors</li>\n<li>Opportunity to attend the EDS/ CASS MQ on Saturday October 3rd.</li>\n<li>Certification of completion</li >\n</ul>\n</div>\n<div><em><strong>Not included:</strong></em></div>\n<div >\n<ul>\n<li>Travel (each applicant is responsible for travel arrangements )</li>\n<li>Visa application fees</li>\n<li>Transportation from and to the airport</li>\n<li>Dinner or additional meals after the sessions</li>\n<li >Incidentals or medical emergency (participants are encouraged to have a m edical insurance)</li>\n</ul>\n<p><img style="display: block\; margin-left : auto\; margin-right: auto\;" src="https://events.vtools.ieee.org/vtools_ ui/media/display/3654dad1-615f-415a-ba3a-87e2996bd0f5" alt="" width="274" height="411"></p>\n</div>\n</div><br /><br />Agenda: <br /><p><strong>Day 1: Thursday\, October 1</strong><br><br>&nbsp\; - 8:30 &ndash\; 9:30 AM: E vent Opening Session (Introduction)<br>&nbsp\; - 9:30 &ndash\; 10:30 AM: D raw a transistor that could be used in a logic gate<br>&nbsp\; - 10:30 AM &ndash\; 12:00 PM: Practice<br>&nbsp\; - 12:00 &ndash\; 1:00 PM: Lunch<br> &nbsp\; - 1:00 &ndash\; 2:00 PM: Build a simple digital design using logic gates<br>&nbsp\; - 2:00 &ndash\; 3:00 PM: Practice<br>&nbsp\; - 3:00 &nda sh\; 3:15 PM: Break<br>&nbsp\; - 3:15 &ndash\; 4:15 PM: Generate the ASIC files from your design<br>&nbsp\; - 4:15 &ndash\; 5:15 PM: Practice<br><br ><strong>Day 2: Friday\, October 2</strong><br><br>&nbsp\; - 9:00 &ndash\; 10:00 AM: Submit your design to be manufactured on the next Tiny Tapeout chip<br>&nbsp\; - 10:00 AM &ndash\; 12:00 PM: Practice<br>&nbsp\; - 12:00 &ndash\; 1:00 PM: Lunch<br>&nbsp\; - 1:00 &ndash\; 4:00 PM: Work on design s &amp\; Q&amp\;A session with instructor</p> END:VEVENT END:VCALENDAR