BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Lisbon BEGIN:DAYLIGHT DTSTART:20260329T020000 TZOFFSETFROM:+0000 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:WEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20261025T010000 TZOFFSETFROM:+0100 TZOFFSETTO:+0000 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:WET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260921T122511Z UID:82816F7C-DF17-4690-862C-3DDB9FD817B8 DTSTART;TZID=Europe/Lisbon:20260917T090000 DTEND;TZID=Europe/Lisbon:20260917T170000 DESCRIPTION:We are pleased to announce the 1st Workshop between UNINOVA Ins titute and the State Key Laboratory of Analog and Mixed-Signal VLSI (SKL-A MSV)\, University of Macau\, dedicated to Advances in Analog & Mixed-Signa l Integrated Circuits.\n\nOrganized by NOVA University of Lisbon and the U niversity of Macau\, this first workshop aims to foster technical exchange \, knowledge sharing and networking between researchers\, academics and pr ofessionals\, strengthening collaboration in the field of analog and mixed -signal integrated circuits. The workshop is powered by POEMS – Portugue se Competence Center in Semiconductors and co-sponsored by IEEE Portugal\, the IEEE CAS-CTSoC-BTS and SSCS Portuguese Chapters\, the Centre for Tech nology and Systems (CTS)\, and NOVA School of Science and Technology (NOVA FCT).\n\nA first step towards stronger collaboration\, knowledge exchange and new opportunities in semiconductor research and innovation.\n\nCo-spo nsored by: Portuguese Competence Centre in Semiconductors (POEMS)\, NOVA S chool of Science and Technology\n\nSpeaker(s): Sai-Weng Sin\, Nuno Paulino \, Mingqiang Guo\, Hugo Serra\, Minglei Zhang\, Mariana Barrosinho\, Hugo Viana\, Man-Kay Law\, Tiago Costa\, Jun Yin\, Luís B. Oliveira\, Wen-Lian g Zeng\, Diogo Dias\, Edgar Albuquerque\n\nAgenda: \nWorkshop Program\n\nM orning: Data-Converters\n\n09h00 The Design of High-Linearity High-Resolut ion Oversampling Incremental ADCs for Sensor Applications\n\n09h30 A 3rd-o rder MASH Switched-Capacitor SDM using Ultra-Incomplete Settling employing an Area Reduction Technique\n\n10h00 Advancements in Dynamic Time-varying Amplifier and Time-Domain Quantization: Voltage/Time Domain Combined ADC Research (remote presentation)\n\n10h30 Beyond the ADC: Integrated Auxilia ry Circuits for a Fully Integrated Mixed-Signal SoC\n\n11h00 My Research J ourney on Time-Domain ADCs (remote presentation)\n\n11h30 Design of High-S peed Analog-to-Digital Converters combining Time-and-Frequency Interleavin g\n\n11h45 A C-2C Charge-Sharing SAR Quantization for Zoom ADCs\n\nAfterno on: Analog and Mixed-Signal ICs and Circuit Techniques\n\n13:30 High effic iency burst power delivery in Miniaturized IoT Systems\n\n14:00 Circuit Te chniques for Power-Efficient Brain Interfaces\n\n14h30 Low-Jitter mm-Wave Frequency Generation\n\n15:00 Hardware Security: Entropy Generation and En cryption\n\n15:30 A general dynamic modeling method for Chiplet power deli very system based on LEGO architecture\n\n16:00 CMOS Ultrasound Imaging Ar chitectures for Wearable Diagnostic Devices (remote presentation)\n\n16:30 A Full Current-Mode AFE with Dark Noise Suppression using Differential Le ading-Edge Discrimination for the CMS/LHC Timing Detector at CERN\n\nRoom: Auditorium\, Bldg: UNINOVA\, Faculdade de Ciências e Tecnologia\, Capari ca\, Lisboa\, Portugal\, 2829-516 LOCATION:Room: Auditorium\, Bldg: UNINOVA\, Faculdade de Ciências e Tecnol ogia\, Caparica\, Lisboa\, Portugal\, 2829-516 ORGANIZER:l.oliveira@fct.unl.pt SEQUENCE:19 SUMMARY:WORKSHOP — Advances in Analog & Mixed-Signal Integrated Circuits URL;VALUE=URI:https://events.vtools.ieee.org/m/577720 X-ALT-DESC:Description: <br /><p>We are pleased to announce the <strong>1st Workshop between UNINOVA Institute and the State Key Laboratory of Analog and Mixed-Signal VLSI (SKL-AMSV)\, University of Macau</strong>\, dedicat ed to <strong>Advances in Analog &amp\; Mixed-Signal Integrated Circuits</ strong>.</p>\n<p>Organized by <strong>NOVA University of Lisbon and the Un iversity of Macau</strong>\, this first workshop aims to foster <strong>te chnical exchange\, knowledge sharing and networking</strong> between resea rchers\, academics and professionals\, strengthening collaboration in the field of analog and mixed-signal integrated circuits.&nbsp\; The workshop is <strong>powered by POEMS &ndash\; Portuguese Competence Center in Semic onductors</strong> and co-sponsored by <strong>IEEE Portugal</strong>\, th e <strong>IEEE CAS-CTSoC-BTS and SSCS Portuguese Chapters</strong>\, the < strong>Centre for Technology and Systems (CTS)</strong>\, and <strong>NOVA School of Science and Technology (NOVA FCT)</strong>.</p>\n<p><strong>A f irst step towards stronger collaboration\, knowledge exchange and new oppo rtunities in semiconductor research and innovation.</strong></p><br /><br />Agenda: <br /><h1><strong>Workshop Program </strong></h1>\n<p><strong>Mo rning: Data-Converters </strong></p>\n<p>09h00 The Design of High-Linearit y High-Resolution Oversampling Incremental ADCs for Sensor Applications&nb sp\;</p>\n<p>09h30 A 3rd-order MASH Switched-Capacitor SDM using Ultra-Inc omplete Settling employing an Area Reduction Technique&nbsp\;</p>\n<p>10h0 0 Advancements in Dynamic Time-varying Amplifier and Time-Domain Quantizat ion: Voltage/Time Domain Combined ADC Research (remote presentation)</p>\n <p>10h30 Beyond the ADC: Integrated Auxiliary Circuits for a Fully Integra ted Mixed-Signal SoC&nbsp\;</p>\n<p>11h00 My Research Journey on Time-Doma in ADCs (remote presentation)&nbsp\;</p>\n<p>11h30 Design of High-Speed An alog-to-Digital Converters combining Time-and-Frequency Interleaving&nbsp\ ;</p>\n<p>11h45 A C-2C Charge-Sharing SAR Quantization for Zoom ADCs&nbsp\ ;</p>\n<p><strong>Afternoon: Analog and Mixed-Signal ICs and Circuit Techn iques</strong></p>\n<p>13:30 High efficiency burst power delivery in Minia turized IoT Systems&nbsp\;</p>\n<p>14:00 Circuit Techniques for Power-Effi cient Brain Interfaces</p>\n<p>14h30 Low-Jitter mm-Wave Frequency Generati on</p>\n<p>15:00 Hardware Security: Entropy Generation and Encryption</p>\ n<p>15:30 A general dynamic modeling method for Chiplet power delivery sys tem based on LEGO architecture</p>\n<p>16:00 &nbsp\;CMOS Ultrasound Imagin g Architectures for Wearable Diagnostic Devices (remote presentation)&nbsp \;</p>\n<p>16:30 A Full Current-Mode AFE with Dark Noise Suppression using Differential Leading-Edge Discrimination for the CMS/LHC Timing Detector at CERN&nbsp\;</p> END:VEVENT END:VCALENDAR