BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Denver BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0700 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:MDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260917T153813Z UID:F40E8E4B-B851-4051-A944-EA429634A6F3 DTSTART;TZID=America/Denver:20260930T180000 DTEND;TZID=America/Denver:20260930T190000 DESCRIPTION:The IEEE Solid-State Circuits Society (SSCS) — Boise Chapter cordially invites you to an upcoming Lecture presented by Dr. Alvin Loke.\ n\nAbstract\n\nDespite the much-debated end of Moore’s Law\, CMOS scalin g still maintains economic relevance — with 2nm gate-all-around SoCs (In tel 18A) already in high-volume manufacturing since January 2026. Area sca ling extensively driven by design/technology innovations co-optimized for logic scaling continues to offer compelling node-to-node power\, performan ce\, area\, and cost benefits.\n\nIn this tutorial\, we will start with a walk through memory lane\, recounting a brief history of transistor evolut ion to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have e nabled FinFET CMOS nodes\, highlighting the resulting technology character istics and challenges. This will set the stage for transitioning to the na noribbon gate-all-around device architecture and unveiling the magic of ho w these devices are fabricated.\n\nCo-sponsored by: IEEE Boise Section\n\n Agenda: \nEvent Details\n\nTitle: The Road to Gate-All-Around CMOS\nSpeake r: Dr. Alvin Loke\, Senior Principal Engineer\, Intel\nDate: Wednesday\, S eptember 30th\nTime: 6:00 PM – 7:00 PM\nLocation: Boise State University \, Room MCMR 105\nFree & Open to All\n\nRoom: 105\, Bldg: MCMR\, Boise Sta te University\, Boise\, Idaho\, United States LOCATION:Room: 105\, Bldg: MCMR\, Boise State University\, Boise\, Idaho\, United States ORGANIZER:thollis@ieee.org SEQUENCE:20 SUMMARY:The Road to Gate-All-Around CMOS URL;VALUE=URI:https://events.vtools.ieee.org/m/578115 X-ALT-DESC:Description: <br /><p>The <strong>IEEE Solid-State Circuits Soci ety (SSCS) &mdash\; Boise Chapter</strong> cordially invites you to an upc oming Lecture presented by <strong>Dr. Alvin Loke</strong>.</p>\n<p><stron g>Abstract</strong></p>\n<p>Despite the much-debated end of Moore&rsquo\;s Law\, CMOS scaling still maintains economic relevance &mdash\; with 2nm g ate-all-around SoCs (Intel 18A) already in high-volume manufacturing since January 2026. Area scaling extensively driven by design/technology innova tions co-optimized for logic scaling continues to offer compelling node-to -node power\, performance\, area\, and cost benefits.</p>\n<p>In this tuto rial\, we will start with a walk through memory lane\, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process tec hnology elements that have enabled FinFET CMOS nodes\, highlighting the re sulting technology characteristics and challenges. This will set the stage for transitioning to the nanoribbon gate-all-around device architecture a nd unveiling the magic of how these devices are fabricated.</p><br /><br / >Agenda: <br /><p><strong>Event Details</strong></p>\n<p><strong>Title: </ strong>The Road to Gate-All-Around CMOS<br><strong>Speaker: </strong>Dr. A lvin Loke\, Senior Principal Engineer\, Intel<br><strong>Date: </strong>We dnesday\, September 30th<br><strong>Time: </strong>6:00 PM &ndash\; 7:00 P M<br><strong>Location: </strong>Boise State University\, Room MCMR 105<br> <strong>Free &amp\; Open to All</strong></p> END:VEVENT END:VCALENDAR