BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
DTSTART:20260308T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20261101T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260926T221145Z
UID:79E77A09-16B8-4ABF-AE5B-E3A09D355CA3
DTSTART;TZID=America/Los_Angeles:20260923T163000
DTEND;TZID=America/Los_Angeles:20260923T173000
DESCRIPTION:As semiconductor scaling faces increasing physical and economic
  challenges\, advanced packaging and heterogeneous integration have become
  key enablers for next-generation AI\, RF\, high-performance computing\, a
 nd wireless systems. In this talk\, Sule Ozev\, Professor at Arizona State
  University and Design Lead for SHIELD USA\, will present the vision\, pro
 gress\, and future roadmap of the SHIELD USA program\, a $100M national in
 itiative focused on developing leap-ahead organic substrate technologies a
 nd strengthening U.S. leadership in advanced semiconductor packaging. The 
 presentation will highlight key innovations demonstrated during Phase 1\, 
 including ultra-high-density planarized wiring\, vertical interconnect blo
 cks (VIBs)\, molded fan-out core technologies\, adaptive defect mitigation
 \, and advanced design enablement flows for large-scale chiplet integratio
 n. Attendees will also gain insight into emerging challenges and opportuni
 ties in package design\, manufacturability\, reliability\, and system-leve
 l optimization for future heterogeneous systems. This seminar will provide
  a unique perspective on how advanced packaging technologies are enabling 
 the next generation of AI\, RF\, and high-performance semiconductor produc
 ts\, while creating new opportunities for innovation across the semiconduc
 tor ecosystem.\n\nThe schedule is as follows:\n\n4.30-5.30 pm PST - Lectur
 e\n\nSpeaker(s): Prof. Sule Ozev\n\nAgenda: \n4.30-5.30 pm PST - Lecture\n
 \nBldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\, Cali
 fornia\, United States\, 92121
LOCATION:Bldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\
 , California\, United States\, 92121
ORGANIZER:vaishnav.srinivas@gmail.com
SEQUENCE:7
SUMMARY:Packaging the Future: Advanced Packaging and Chiplet Integration th
 rough ASU SHIELD USA
URL;VALUE=URI:https://events.vtools.ieee.org/m/579064
X-ALT-DESC:Description: <br /><p class="xmsonormal"><em><span style="font-s
 ize: 11.0pt\; color: black\;">As semiconductor scaling faces increasing ph
 ysical and economic challenges\, advanced packaging and heterogeneous inte
 gration have become key enablers for next-generation AI\, RF\, high-perfor
 mance computing\, and wireless systems. In this talk\, Sule Ozev\, Profess
 or at Arizona State University and Design Lead for SHIELD USA\, will prese
 nt the vision\, progress\, and future roadmap of the SHIELD USA program\, 
 a $100M national initiative focused on developing leap-ahead organic subst
 rate technologies and strengthening U.S. leadership in advanced semiconduc
 tor packaging. </span></em><em><span style="font-size: 11.0pt\; color: bla
 ck\;">The presentation will highlight key innovations demonstrated during 
 Phase 1\, including ultra-high-density planarized wiring\, vertical interc
 onnect blocks (VIBs)\, molded fan-out core technologies\, adaptive defect 
 mitigation\, and advanced design enablement flows for large-scale chiplet 
 integration. Attendees will also gain insight into emerging challenges and
  opportunities in package design\, manufacturability\, reliability\, and s
 ystem-level optimization for future heterogeneous systems. </span></em><em
 ><span style="font-size: 11.0pt\; color: black\;">This seminar will provid
 e a unique perspective on how advanced packaging technologies are enabling
  the next generation of AI\, RF\, and high-performance semiconductor produ
 cts\, while creating new opportunities for innovation across the semicondu
 ctor ecosystem.</span></em></p>\n<p style="text-align: justify\;">The sche
 dule is as follows:&nbsp\;</p>\n<p>4.30-5.30 pm PST - Lecture</p><br /><br
  />Agenda: <br /><p>4.30-5.30 pm PST - Lecture</p>
END:VEVENT
END:VCALENDAR