BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20261028T235445Z UID:E280D88E-6512-4CC0-A7DC-7B6980E5425E DTSTART;TZID=America/New_York:20261026T183000 DTEND;TZID=America/New_York:20261026T203000 DESCRIPTION:The relentless demand for multi-gigabit wireless communication and high-resolution sensing\ndrives rapid innovation in D-band (110–170 GHz) systems. However\, realizing efficient and\nscalable active phased ar rays at these frequencies remains challenging due to high cost\,\nintercon nect losses\, packaging parasitics\, and heterogeneous integration constra ints. This\ntalk presents a holistic\, system-level approach to low-loss D -band phased array integration\nthat unifies circuit\, antenna\, and packa ging co-design. Leveraging both silicon-based\n(CMOS\, SiGe) and III–V i ntegrated circuits\, the approach emphasizes optimized\nbeamformer and pow er amplifier architectures combined with low-cost 2D scalable\, wide-\nang le scanning wideband antenna arrays implemented using low-cost PCB process es.\nThrough electromagnetic co-optimization and advanced interconnect eng ineering\, the\nframework achieves significant reduction in loss and impro vement in overall system\nefficiency. Measured D-band results from prototy pe modules demonstrate wide-angle beam\nsteering and data transmission rat es up to 100 Gb/s. These results confirm the feasibility of\nsteerable\, h igh-capacity arrays suitable for both communication and sensing platforms. \n\nSpeaker(s): Dr Kamil Kapusuz\, \n\nAgenda: \n6:30pm Introduction of Sp eaker\n\n6:35pm-7:20pm Presentation\n\n7:20pm-7:40pm Q&A\n\n7:40pm-7:45pm Closing\n\n7:45pm-8:30pm Dinner\n\nRoom: Meeting room with project - withi n library\, Bldg: Bell Works Building\, 101 Crawfords Corner Road\, Librar y meeting room\, Holmdel\, New Jersey\, United States\, 07733\, Virtual: h ttps://events.vtools.ieee.org/m/579742 LOCATION:Room: Meeting room with project - within library\, Bldg: Bell Work s Building\, 101 Crawfords Corner Road\, Library meeting room\, Holmdel\, New Jersey\, United States\, 07733\, Virtual: https://events.vtools.ieee.o rg/m/579742 ORGANIZER:sharmaneerja100@gmail.com SEQUENCE:68 SUMMARY:From Chip to System: A Holistic Approach to 2D Scalable Low-Loss D- Band Active Phased Array Realization URL;VALUE=URI:https://events.vtools.ieee.org/m/579742 X-ALT-DESC:Description: <br /><p>The relentless demand for multi-gigabit wi reless communication and high-resolution sensing<br>drives rapid innovatio n in D-band (110&ndash\;170 GHz) systems. However\, realizing efficient an d<br>scalable active phased arrays at these frequencies remains challengin g due to high cost\,<br>interconnect losses\, packaging parasitics\, and h eterogeneous integration constraints. This<br>talk presents a holistic\, s ystem-level approach to low-loss D-band phased array integration<br>that u nifies circuit\, antenna\, and packaging co-design. Leveraging both silico n-based<br>(CMOS\, SiGe) and III&ndash\;V integrated circuits\, the approa ch emphasizes optimized<br>beamformer and power amplifier architectures co mbined with low-cost 2D scalable\, wide-<br>angle scanning wideband antenn a arrays implemented using low-cost PCB processes.<br>Through electromagne tic co-optimization and advanced interconnect engineering\, the<br>framewo rk achieves significant reduction in loss and improvement in overall syste m<br>efficiency. Measured D-band results from prototype modules demonstrat e wide-angle beam<br>steering and data transmission rates up to 100 Gb/s. These results confirm the feasibility of<br>steerable\, high-capacity arra ys suitable for both communication and sensing platforms.</p><br /><br />A genda: <br /><p>6:30pm Introduction of Speaker</p>\n<p>6:35pm-7:20pm Prese ntation</p>\n<p>7:20pm-7:40pm Q&amp\;A</p>\n<p>7:40pm-7:45pm Closing</p>\n <p>7:45pm-8:30pm Dinner</p> END:VEVENT END:VCALENDAR