BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Paris BEGIN:DAYLIGHT DTSTART:20260329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20261025T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260925T072519Z UID:F076353D-3D04-4759-9B6D-4004458BAB42 DTSTART;TZID=Europe/Paris:20261015T110000 DTEND;TZID=Europe/Paris:20261015T115500 DESCRIPTION:High-performance computing based on the von Neumann architectur e is facing increasing power and energy-efficiency challenges. Cryogenic c omputing\, spanning von Neumann\, neuromorphic\, and quantum systems\, has emerged as a promising approach to enable highly energy-efficient data pr ocessing. CMOS technology remains a key platform for implementing these sy stems\, but conventional devices optimized for room-temperature operation face fundamental challenges at cryogenic temperatures. As the temperature approaches absolute zero\, the subthreshold swing (SS) becomes increasingl y limited by band-tail effects\, while the threshold voltage increases due to bandgap widening and Fermi-level shifts. These effects degrade transis tor performance and pose significant challenges for low-power circuit oper ation and design.\n\nThis presentation discusses the key physical and tech nological challenges of cryogenic CMOS and explores device and material st rategies for overcoming these limitations. In addition\, the feasibility o f cryogenic memory based on a single fully depleted silicon-on-insulator ( FDSOI) MOSFET will be presented. By integrating memory and logic functiona lities within a CMOS-compatible platform\, this work points toward highly energy-efficient and scalable computing systems operating at cryogenic tem peratures.\n\nCo-sponsored by: INPACE\, SINANO\n\nSpeaker(s): Qing-Tai Zha o \, \n\nVirtual: https://events.vtools.ieee.org/m/579823 LOCATION:Virtual: https://events.vtools.ieee.org/m/579823 ORGANIZER:francis.balestra@grenoble-inp.fr SEQUENCE:23 SUMMARY:Webinar – Toward low power cryogenic Si MOSFETs URL;VALUE=URI:https://events.vtools.ieee.org/m/579823 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\; line-height: normal\; background: white\; vertical-align: baseline\; margin: 10.2pt 0cm 10.2pt 0cm\;"><span lang="EN-GB" style="font-size: 10.5 pt\; font-family: 'inherit'\,serif\; mso-fareast-font-family: 'Times New R oman'\; mso-bidi-font-family: Helvetica\; color: #666666\; mso-font-kernin g: 0pt\; mso-ligatures: none\; mso-ansi-language: EN-GB\; mso-fareast-lang uage: FR\;">High-performance computing based on the von Neumann architectu re is facing increasing power and energy-efficiency challenges. Cryogenic computing\, spanning von Neumann\, neuromorphic\, and quantum systems\, ha s emerged as a promising approach to enable highly energy-efficient data p rocessing. CMOS technology remains a key platform for implementing these s ystems\, but conventional devices optimized for room-temperature operation face fundamental challenges at cryogenic temperatures. As the temperature approaches absolute zero\, the subthreshold swing (SS) becomes increasing ly limited by band-tail effects\, while the threshold voltage increases du e to bandgap widening and Fermi-level shifts. These effects degrade transi stor performance and pose significant challenges for low-power circuit ope ration and design.</span></p>\n<p class="MsoNormal" style="text-align: jus tify\; line-height: normal\; background: white\; vertical-align: baseline\ ; margin: 10.2pt 0cm 10.2pt 0cm\;"><span lang="EN-GB" style="font-size: 10 .5pt\; font-family: 'inherit'\,serif\; mso-fareast-font-family: 'Times New Roman'\; mso-bidi-font-family: Helvetica\; color: #666666\; mso-font-kern ing: 0pt\; mso-ligatures: none\; mso-ansi-language: EN-GB\; mso-fareast-la nguage: FR\;">&nbsp\;</span><span lang="EN-GB" style="font-size: 10.5pt\; font-family: 'inherit'\,serif\; mso-fareast-font-family: 'Times New Roman' \; mso-bidi-font-family: Helvetica\; color: #666666\; mso-font-kerning: 0p t\; mso-ligatures: none\; mso-ansi-language: EN-GB\; mso-fareast-language: FR\;">This presentation discusses the key physical and technological chal lenges of cryogenic CMOS and explores device and material strategies for o vercoming these limitations. In addition\, the feasibility of cryogenic me mory based on a single fully depleted silicon-on-insulator (FDSOI) MOSFET will be presented. By integrating memory and logic functionalities within a CMOS-compatible platform\, this work points toward highly energy-efficie nt and scalable computing systems operating at cryogenic temperatures.</sp an></p> END:VEVENT END:VCALENDAR