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DESCRIPTION:Moore’s Law\, six decades ago\, set the course of complementa
 ry metal oxide semiconductor (CMOS) scaling\, and its pace has essentially
  been dictated by dimensional reduction of device size. Then node-to-node 
 performance improvements at fixed power\, based on PPA (power-performance-
 area) efficiency – referred to as Dennard scaling started. The strong re
 duction in gate length and width led to an increase in off state leakage c
 urrent and lower Ion/Ioff ratio. These short channel effects have driven t
 echnology to transition from planar MOSFETs to FinFETs\, and recently\, to
  gate-all-around (GAA) nanosheet (NS) transistors for high-performance com
 puting applications. The scaling has led to larger effective widths per un
 it footprint area. Further promising structures are vertically stacked nan
 osheets and complementary field effect transistors (CFETs). In a CFET conf
 iguration\, NMOS with Si channel and PMOS with SiGe channel devices are ve
 rtically stacked realized using multilayer epitaxial depositions and selec
 tive etchings. These advancements require innovations in device architectu
 re\, material & process engineering and design technology co-optimization 
 (DTCO) when combined at standard cell level. These include\, among others\
 , advanced interconnect and middle-of-line schemes and the introduction of
  backside power delivery network (BSPDN). While the electrical and density
  improvements of CFET are undeniable\, the architecture is accompanied by 
 a new variety of challenges. Additionally\, heat dissipation becomes a pro
 minent issue. As more research is conducted on CFETs\, more effective solu
 tions will be implemented to address these challenges.\n\nSpeaker(s): Dr. 
 Santosh K. Kurinec\, \n\nVirtual: https://events.vtools.ieee.org/m/581507
LOCATION:Virtual: https://events.vtools.ieee.org/m/581507
ORGANIZER:minhaz.eee.cuet@gmail.com
SEQUENCE:1
SUMMARY:CMOS Scaling to Sub-nm Stacked CFETs
URL;VALUE=URI:https://events.vtools.ieee.org/m/581507
X-ALT-DESC:Description: <br /><p>Moore&rsquo\;s Law\, six decades ago\, set
  the course of complementary metal oxide semiconductor (CMOS) scaling\, an
 d its pace has essentially been dictated by dimensional reduction of devic
 e size. Then node-to-node performance improvements at fixed power\, based 
 on PPA (power-performance-area) efficiency &ndash\; referred to as Dennard
  scaling started. The strong reduction in gate length and width led to an 
 increase in off state leakage current and lower Ion/Ioff ratio. These shor
 t channel effects have driven technology to transition from planar MOSFETs
  to FinFETs\, and recently\, to gate-all-around (GAA) nanosheet (NS) trans
 istors for high-performance computing applications. The scaling has led to
  larger effective widths per unit footprint area. Further promising struct
 ures are vertically stacked nanosheets and complementary field effect tran
 sistors (CFETs). In a CFET configuration\, NMOS with Si channel and PMOS w
 ith SiGe channel devices are vertically stacked realized using multilayer 
 epitaxial depositions and selective etchings. These advancements require i
 nnovations in device architecture\, material &amp\; process engineering an
 d design technology co-optimization (DTCO) when combined at standard cell 
 level. These include\, among others\, advanced interconnect and middle-of-
 line schemes and the introduction of backside power delivery network (BSPD
 N). While the electrical and density improvements of CFET are undeniable\,
  the architecture is accompanied by a new variety of challenges. Additiona
 lly\, heat dissipation becomes a prominent issue. As more research is cond
 ucted on CFETs\, more effective solutions will be implemented to address t
 hese challenges.</p>
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