BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
DTSTART:20260308T030000
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:EDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20261101T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20261002T161607Z
UID:81904718-32F1-42DD-B645-DE4FD55FB6D4
DTSTART;TZID=America/New_York:20261021T160000
DTEND;TZID=America/New_York:20261021T170000
DESCRIPTION:Please join us for an upcoming seminar by Dr. Rubaiyat Islam\, 
 AMD Fellow at Advanced Micro Devices (AMD).\n\nDate: Wednesday\, 21 Octobe
 r 2026\n\nTime: 4 – 5 pm (ET)\n\nLocation: University of Toronto\, Room 
 UC 161\, University College (Main Building)\, 15 King&#39;s College Circle\, T
 oronto\, ON M5S 3H7\n\nThis event is supported by the IEEE AP-S Technical 
 Committee on Electromagnetics and Fundamentals (TC5) and the IEEE Toronto 
 Section.\n\nAbstract:\n\nElectromagnetics and microwave circuit principles
  have long guided the art of designing substrates for packaging silicon ch
 ips. The chip package not only enables high-speed signals to propagate bey
 ond the die but also delivers the power required for operation. With ever-
 increasing data rates and channel densities in SerDes and memory systems\,
  along with the growing power demands of digital blocks in modern AI accel
 erators and CPUs\, new package design challenges have emerged.\n\nThis pre
 sentation will introduce Signal and Power Integrity (SI/PI) analysis in ch
 ip design by outlining key technical challenges\, solution methodologies\,
  and software tool development at AMD. Today\, SI/PI has evolved into a mu
 ltidisciplinary field encompassing electromagnetics\, circuit design\, con
 trol systems\, physical design\, thermal and mechanical engineering\, as w
 ell as manufacturing and yield optimization. This convergence of disciplin
 es is driving innovation not only in design methodologies but also in Elec
 tronic Design Automation (EDA) software tools.\n\nBiography:\n\nRubaiyat I
 slam received his BASc in Engineering Science in 2002 and his PhD in Elect
 romagnetics in 2011 from the University of Toronto. In 2011\, he joined Ad
 vanced Micro Devices (AMD) as a Senior Analog Design Engineer in the Signa
 l Integrity Group. From 2020 to 2024\, he served as a Principal Engineer a
 t AMD\, leading the development of multiple Signal and Power Integrity (SI
 /PI) Electronic Design Automation (EDA) software tools that are used in pr
 oduction workflows by both AMD internal teams and external customers. Curr
 ently\, he is an AMD Fellow\, with research and development interests in S
 I/PI for high-speed wireline communication systems\, power delivery networ
 ks and voltage regulation\, as well as electro-optical signal transmission
 .\n\nSpeaker(s): Rubaiyat Islam\, \n\nRoom: UC 161\, Bldg: University Coll
 ege (Main Building)\, 15 King&#39;s College Circle\, Toronto\, Ontario\, Canad
 a\, M5S 3H7
LOCATION:Room: UC 161\, Bldg: University College (Main Building)\, 15 King&#39;
 s College Circle\, Toronto\, Ontario\, Canada\, M5S 3H7
ORGANIZER:mantoniades@torontomu.ca
SEQUENCE:7
SUMMARY:[IEEE AP-S Seminar] Signal and Power Integrity in Chip Development
URL;VALUE=URI:https://events.vtools.ieee.org/m/581572
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0
 001pt\; text-align: justify\; line-height: normal\; layout-grid-mode: char
 \; mso-layout-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.
 0pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\
 ; mso-bidi-font-weight: bold\;&quot;&gt;Please join us for an upcoming seminar by 
 Dr. Rubaiyat Islam\, AMD Fellow at Advanced Micro Devices (AMD).&lt;/span&gt;&lt;/p
 &gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001pt\; text-align: justif
 y\; line-height: normal\; layout-grid-mode: char\; mso-layout-grid-align: 
 none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;
 \,sans-serif\; mso-fareast-font-family: Calibri\; mso-bidi-font-weight: bo
 ld\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001
 pt\; text-align: justify\; line-height: normal\; layout-grid-mode: char\; 
 mso-layout-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt
 \; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\; m
 so-bidi-font-weight: bold\;&quot;&gt;Date: Wednesday\, 21 October 2026&lt;/span&gt;&lt;/p&gt;\
 n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001pt\; text-align: justify\
 ; line-height: normal\; layout-grid-mode: char\; mso-layout-grid-align: no
 ne\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\,
 sans-serif\; mso-fareast-font-family: Calibri\; mso-bidi-font-weight: bold
 \;&quot;&gt;Time: 4 &amp;ndash\; 5 pm (ET)&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;mar
 gin-bottom: .0001pt\; text-align: justify\; line-height: normal\; layout-g
 rid-mode: char\; mso-layout-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;
 font-size: 12.0pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-fa
 mily: Calibri\; mso-bidi-font-weight: bold\;&quot;&gt;Location: University of Toro
 nto\, Room UC 161\, University College (Main Building)\, 15 King&#39;s College
  Circle\, Toronto\, ON M5S 3H7&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;mar
 gin-bottom: .0001pt\; text-align: justify\; line-height: normal\; layout-g
 rid-mode: char\; mso-layout-grid-align: none\;&quot;&gt;&lt;strong style=&quot;mso-bidi-fo
 nt-weight: normal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-fa
 mily: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\;&quot;&gt;&amp;nbsp\;&lt;/s
 pan&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001pt\; te
 xt-align: justify\; line-height: normal\; layout-grid-mode: char\; mso-lay
 out-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font
 -family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\;&quot;&gt;This ev
 ent is supported by the &lt;strong style=&quot;mso-bidi-font-weight: normal\;&quot;&gt;IEE
 E AP-S Technical Committee on Electromagnetics and Fundamentals (TC5)&lt;/str
 ong&gt; and the &lt;strong style=&quot;mso-bidi-font-weight: normal\;&quot;&gt;IEEE Toronto S
 ection&lt;/strong&gt;.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0
 001pt\; text-align: justify\; line-height: normal\; layout-grid-mode: char
 \; mso-layout-grid-align: none\;&quot;&gt;&lt;strong style=&quot;mso-bidi-font-weight: nor
 mal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\
 ,sans-serif\; mso-fareast-font-family: Calibri\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/strong&gt;&lt;
 /p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; text-indent: -18.0p
 t\; line-height: normal\; layout-grid-mode: char\; mso-layout-grid-align: 
 none\; margin: 0cm 0cm .0001pt 18.0pt\;&quot;&gt;&lt;strong style=&quot;mso-bidi-font-weig
 ht: normal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;
 Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\;&quot;&gt;Abstract:&lt;/span&gt;&lt;
 /strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001pt\; text-al
 ign: justify\; line-height: normal\; layout-grid-mode: char\; mso-layout-g
 rid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-fami
 ly: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;El
 ectromagnetics and microwave circuit principles have long guided the art o
 f designing substrates for packaging silicon chips. The chip package not o
 nly enables high-speed signals to propagate beyond the die but also delive
 rs the power required for operation. With ever-increasing data rates and c
 hannel densities in SerDes and memory systems\, along with the growing pow
 er demands of digital blocks in modern AI accelerators and CPUs\, new pack
 age design challenges have emerged.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style
 =&quot;margin-bottom: .0001pt\; text-align: justify\; line-height: normal\; lay
 out-grid-mode: char\; mso-layout-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; st
 yle=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-fo
 nt-family: &#39;Times New Roman&#39;\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; s
 tyle=&quot;margin-bottom: .0001pt\; text-align: justify\; line-height: normal\;
  layout-grid-mode: char\; mso-layout-grid-align: none\;&quot;&gt;&lt;span lang=&quot;EN-CA
 &quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareas
 t-font-family: &#39;Times New Roman&#39;\;&quot;&gt;This presentation will introduce Signa
 l and Power Integrity (SI/PI) analysis in chip design by outlining key tec
 hnical challenges\, solution methodologies\, and software tool development
  at AMD. Today\, SI/PI has evolved into a multidisciplinary field encompas
 sing electromagnetics\, circuit design\, control systems\, physical design
 \, thermal and mechanical engineering\, as well as manufacturing and yield
  optimization. This convergence of disciplines is driving innovation not o
 nly in design methodologies but also in Electronic Design Automation (EDA)
  software tools.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0
 001pt\; text-align: justify\; line-height: normal\; layout-grid-mode: char
 \; mso-layout-grid-align: none\;&quot;&gt;&lt;strong style=&quot;mso-bidi-font-weight: nor
 mal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\
 ,sans-serif\; mso-fareast-font-family: Calibri\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/strong&gt;&lt;
 /p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: .0001pt\; text-align: just
 ify\; line-height: normal\; layout-grid-mode: char\; mso-layout-grid-align
 : none\;&quot;&gt;&lt;strong style=&quot;mso-bidi-font-weight: normal\;&quot;&gt;&lt;span lang=&quot;EN-CA
 &quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareas
 t-font-family: Calibri\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal
 &quot; style=&quot;margin-bottom: .0001pt\; text-align: justify\; line-height: norma
 l\; layout-grid-mode: char\; mso-layout-grid-align: none\;&quot;&gt;&lt;strong style=
 &quot;mso-bidi-font-weight: normal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0
 pt\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: Calibri\;
 &quot;&gt;Biography:&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 
 12.0pt\; line-height: 107%\; font-family: &#39;Arial&#39;\,sans-serif\; mso-fareas
 t-font-family: Calibri\; mso-ansi-language: EN-CA\; mso-fareast-language: 
 EN-US\; mso-bidi-language: AR-SA\; mso-bidi-font-weight: bold\;&quot;&gt;Rubaiyat 
 Islam received his BASc in Engineering Science in 2002 and his PhD in Elec
 tromagnetics in 2011 from the University of Toronto. In 2011\, he joined A
 dvanced Micro Devices (AMD) as a Senior Analog Design Engineer in the Sign
 al Integrity Group. From 2020 to 2024\, he served as a Principal Engineer 
 at AMD\, leading the development of multiple Signal and Power Integrity (S
 I/PI) Electronic Design Automation (EDA) software tools that are used in p
 roduction workflows by both AMD internal teams and external customers. Cur
 rently\, he is an AMD Fellow\, with research and development interests in 
 SI/PI for high-speed wireline communication systems\, power delivery netwo
 rks and voltage regulation\, as well as electro-optical signal transmissio
 n.&lt;/span&gt;&lt;/p&gt;
END:VEVENT
END:VCALENDAR