BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20261004T085913Z
UID:3ADC289F-904C-4672-B18B-4C3AA428DBBD
DTSTART;TZID=Asia/Kolkata:20261010T130000
DTEND;TZID=Asia/Kolkata:20261011T170000
DESCRIPTION:The student will design a multi-layer PCB for IoT application\n
 \nCo-sponsored by: Shri Sant Gajanan Maharaj College of Engineering Shegao
 n\n\nSpeaker(s): Shri\n\nAgenda: \n- Circuit design and Simulation\n- Sing
 le PCB Design upto garbar file\n- Multi-Layer PCB Design\n\nBldg: VLSI Lab
 \, Shri Sant Gajanan Maharaj College of engineering\, EXTC Department\, Sh
 egaon\, Maharashtra\, India\, 444203
LOCATION:Bldg: VLSI Lab\, Shri Sant Gajanan Maharaj College of engineering\
 , EXTC Department\, Shegaon\, Maharashtra\, India\, 444203
ORGANIZER:vkbhangdiya@gmail.com
SEQUENCE:10
SUMMARY:PCB Design Workshop 
URL;VALUE=URI:https://events.vtools.ieee.org/m/582160
X-ALT-DESC:Description: <br /><p>The student will design a multi-layer PCB 
 for IoT application</p><br /><br />Agenda: <br /><ol>\n<li>Circuit design 
 and Simulation</li>\n<li>Single PCB Design upto garbar file</li>\n<li>Mult
 i-Layer PCB Design</li>\n</ol>
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