BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20261021T234534Z UID:44EB246B-01AC-4FF4-B51A-BDC2FF5AB627 DTSTART;TZID=America/Los_Angeles:20261020T160000 DTEND;TZID=America/Los_Angeles:20261020T180000 DESCRIPTION:The fields of advanced packaging and heterogeneous integration (APHI) have evolved at an unprecedented rate of innovation in recent years . This has been driven by two key driving factors: integrated circuit chip lets and AI compute needs. Together\, these have driven the industry towar ds adopting package-level interconnect and bonding processes that are blur ring the boundary between on-chip and off-chip interconnects\, ever larger package substrates\, 3D stacking\, liquid cooling solutions\, advanced po wer delivery architectures\, and photonic I/Os. In this presentation\, we will first review recent industry trends in APHI. Next\, we will present o ur research in designing and fabricating passive-chiplets to build package functions that enable higher levels of integration density and performanc e\, including cooling chiplets for 3D ICs that feature monolithic microflu idic cooling channels with high density through-silicon-vias\, fiber-attac h chiplets that self-align a bundle of fibers to a photonic integrated cir cuit at high precision\, and mm-wave interconnect chiplets that provide br oadband and low-loss connectivity for MMICs. Further\, we will present adv ances in large area glass-core package substrates\, including co-packaged optics. The schedule is as follows:\n\n4-4.30 pm - Networking\n\n4.30-6 pm - Lecture\n\nSpeaker(s): Prof. Muhannad Bakir\n\nAgenda: \n4-4.30 pm - Ne tworking\n\n4.30-6 pm - Lecture\n\nBldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\, California\, United States\, 92121 LOCATION:Bldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\ , California\, United States\, 92121 ORGANIZER:vaishnav.srinivas@gmail.com SEQUENCE:13 SUMMARY:Heterogeneous Integration Technologies for AI System Scaling: Redef ining Interconnects\, Cooling and 3D Integration URL;VALUE=URI:https://events.vtools.ieee.org/m/583030 X-ALT-DESC:Description: <br /><p style="text-align: justify\;">The fields o f advanced packaging and heterogeneous integration (APHI) have evolved at an unprecedented rate of innovation in recent years. This has been driven by two key driving factors: integrated circuit chiplets and AI compute nee ds. Together\, these have driven the industry towards adopting package-lev el interconnect and bonding processes that are blurring the boundary betwe en on-chip and off-chip interconnects\, ever larger package substrates\, 3 D stacking\, liquid cooling solutions\, advanced power delivery architectu res\, and photonic I/Os. In this presentation\, we will first review recen t industry trends in APHI. Next\, we will present our research in designin g and fabricating passive-chiplets to build package functions that enable higher levels of integration density and performance\, including cooling c hiplets for 3D ICs that feature monolithic microfluidic cooling channels w ith high density through-silicon-vias\, fiber-attach chiplets that self-al ign a bundle of fibers to a photonic integrated circuit at high precision\ , and mm-wave interconnect chiplets that provide broadband and low-loss co nnectivity for MMICs. Further\, we will present advances in large area gla ss-core package substrates\, including co-packaged optics. The schedule is as follows:&nbsp\;</p>\n<p>4-4.30 pm - Networking</p>\n<p>4.30-6 pm - Lec ture</p><br /><br />Agenda: <br /><p>4-4.30 pm - Networking</p>\n<p>4.30-6 pm - Lecture</p> END:VEVENT END:VCALENDAR