BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20261008T052916Z
UID:52C0055F-DAF2-45D8-A2B3-FE3F4A022674
DTSTART;TZID=Asia/Kolkata:20261011T100000
DTEND;TZID=Asia/Kolkata:20261011T120000
DESCRIPTION:[]\n\nCo-sponsored by: Vellore Institute of Technology\, Chenna
 i\n\nAgenda: \nThis talk will explore key high-speed analog layout techniq
 ues for achieving performance\, matching\, and reliability. Topics include
  floorplanning\, common-centroid\, interdigitation\, symmetry\, dummy devi
 ces\, multi-fingering\, shielding\, guard rings\, substrate isolation\, di
 fferential routing\, critical-net routing\, power and ground planning\, pa
 rasitic minimization\, IR-drop and electromigration control. The session a
 lso highlights challenges in advanced technology nodes\, including process
  variation\, reduced supply voltage\, increased device density\, and paras
 itic effects on high-speed analog circuit performance.\n\nVirtual: https:/
 /events.vtools.ieee.org/m/583168
LOCATION:Virtual: https://events.vtools.ieee.org/m/583168
ORGANIZER:pritam_bhattacharjee@live.com
SEQUENCE:54
SUMMARY:Technical Talk on "Analog Layout for High-Speed Circuits".
URL;VALUE=URI:https://events.vtools.ieee.org/m/583168
X-ALT-DESC:Description: <br /><p><img src="https://events.vtools.ieee.org/v
 tools_ui/media/display/6f96a004-d639-494c-b4fc-d69a19ab05e1" alt="" width=
 "928" height="1600"></p><br /><br />Agenda: <br /><p style="text-align: ju
 stify\;"><span style="color: #0000ff\;">This talk will explore key high-sp
 eed analog layout techniques for achieving performance\, matching\, and re
 liability. Topics include floorplanning\, common-centroid\, interdigitatio
 n\, symmetry\, dummy devices\, multi-fingering\, shielding\, guard rings\,
  substrate isolation\, differential routing\, critical-net routing\, power
  and ground planning\, parasitic minimization\, IR-drop and electromigrati
 on control. The session also highlights challenges in advanced technology 
 nodes\, including process variation\, reduced supply voltage\, increased d
 evice density\, and parasitic effects on high-speed analog circuit perform
 ance</span>.</p>
END:VEVENT
END:VCALENDAR