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DTSTART:20380119T084407
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BEGIN:VEVENT
DTSTAMP:20261009T154845Z
UID:68E1A472-04FB-4ADE-9238-B2FC30135B8B
DTSTART;TZID=Asia/Colombo:20261014T101500
DTEND;TZID=Asia/Colombo:20261014T120000
DESCRIPTION:This session is proudly organized as part of the IEEE Day 2026 
 celebrations at the University of Peradeniya.\nJoin us for a hands-on work
 shop on hardware acceleration focusing on Xilinx FPGA boards. Professional
  skills covered include:\n\n-\nFundamentals of RTL and digital logic desig
 n\n\n-\nFPGA synthesis and hardware acceleration\n\n-\nFunctional verifica
 tion and performance analysis\n\n-\nFPGA deployment and toolchain implemen
 tation\n\nSpeaker(s): Mr. Kavinga Upul Ekanayake\n\nBldg: Drawing Office I
 I\, Faculty of Engineering\, University of Peradeniya\, Peradeniya\, Sri L
 anka\, Sri Lanka\, 20400
LOCATION:Bldg: Drawing Office II\, Faculty of Engineering\, University of P
 eradeniya\, Peradeniya\, Sri Lanka\, Sri Lanka\, 20400
ORGANIZER:ieeepdn@gmail.com
SEQUENCE:28
SUMMARY:Code to Chip: Build & Accelerate with FPGAs
URL;VALUE=URI:https://events.vtools.ieee.org/m/583816
X-ALT-DESC:Description: <br /><p data-path-to-node="2\,4\,0"><strong data-p
 ath-to-node="2\,4\,0" data-index-in-node="19">This session is proudly orga
 nized as part of the IEEE Day 2026 celebrations at the University of Perad
 eniya.</strong> <br>Join us for a hands-on workshop on hardware accelerati
 on focusing on Xilinx FPGA boards. Professional skills covered include:</p
 >\n<ul data-path-to-node="2\,4\,1">\n<li>\n<p data-path-to-node="2\,4\,1\,
 0\,0">Fundamentals of RTL and digital logic design</p>\n</li>\n<li>\n<p da
 ta-path-to-node="2\,4\,1\,1\,0">FPGA synthesis and hardware acceleration</
 p>\n</li>\n<li>\n<p data-path-to-node="2\,4\,1\,2\,0">Functional verificat
 ion and performance analysis</p>\n</li>\n<li>\n<p data-path-to-node="2\,4\
 ,1\,3\,0">FPGA deployment and toolchain implementation</p>\n</li>\n</ul>
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