BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0600 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20261019T185427Z UID:19335391-AAFC-4DE7-936A-E1D16DE9F56C DTSTART;TZID=America/Chicago:20261016T130000 DTEND;TZID=America/Chicago:20261016T140000 DESCRIPTION:Speaker:\n\nDr. Ching-Tzu Chen\, IBM\n\nTime:\n\nOctober 16\, 1 pm-2pm\n\nOnline link:\n\nhttps://gcc02.safelinks.protection.outlook.com/? url=https%3A%2F%2Furldefense.us%2Fv3%2F__https%3A%2F%2Fteams.microsoft.com %2Fl%2Fmeetup-join%2F19*3ameeting_NzBkOThiY2UtN2NkYi00ODcxLThhOGItYWYyOWE4 YTQ1NzY0*40thread.v2%2F0%3Fcontext%3D*7b*22Tid*22*3a*220cfca185-25f7-49e3- 8ae7-704d5326e285*22*2c*22Oid*22*3a*22a8ae4553-86d9-421a-82d0-c175112acee8 *22*7d__%3BJSUlJSUlJSUlJSUlJSUl!!G_uCfscf7eWS!faGZNgevT4W_ufn1sHk4l_w3Kllw 6CYpaShGFk_bggnWzgHq3LdKiott3ukX3ah3-9pHXoL9lFkiR16_JqFBSr7e1QeYLFjFsw%24& data=05%7C02%7Cyili%40anl.gov%7C01b855f47ff14780e81e08df261c4f29%7C0cfca18 525f749e38ae7704d5326e285%7C0%7C0%7C639271575166260823%7CUnknown%7CTWFpbGZ sb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiT WFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=Mwe9QI86leIrgCcbyZe7Tobc4FzEfuZ xTqoUCmW1xv0%3D&reserved=0\n\nPunchline:\n\nLeveraging fundamentally new e lectronic structures\, back-end-of-line (BEOL) interconnects with novel co nductors can revert the rising resistivity in nanoscale wiring and overcom e the BEOL performance scaling bottleneck.\n\nAbstract:\n\nResistivity of conventional metals\, such as Cu and Ru\, increases sharply below 20 nm. C onsequently\, Cu interconnect scaling has become a key performance bottlen eck in advanced-node integrated circuits. In this talk\, we first introduc e the fundamentals for the interconnect technologies and discuss the root cause of the scaling bottleneck. We then explore how the resistivity incre ase can be mitigated or even reverted by adopting novel conductors\, namel y\, topological and anisotropic conductors. From theoretical simulations t o hardware demos\, we present the proof-of-concept verification of reverse d resistivity scaling using topological Cosi nanowires at 8” wafer scale \, showing that the predicted topological-surface-state physics can surviv e CMOS processing. We further survey the current research landscape and di scuss the urgent need for high-throughput screening with examples. We will conclude with a list of requirements to help guide the search for best co nductor candidates.\n\nLemont\, Illinois\, United States\, Virtual: https: //events.vtools.ieee.org/m/586069 LOCATION:Lemont\, Illinois\, United States\, Virtual: https://events.vtools .ieee.org/m/586069 ORGANIZER:yili@anl.gov SEQUENCE:12 SUMMARY:Tackling the Interconnect Scaling Bottleneck with Novel Conductors URL;VALUE=URI:https://events.vtools.ieee.org/m/586069 X-ALT-DESC:Description: <br /><p><strong>Speaker</strong>:</p>\n<p><span da ta-olk-copy-source="MessageBody">Dr.&nbsp\;</span>Ching-Tzu Chen\, IBM</p> \n<p><strong>Time</strong>:</p>\n<p>October 16\, 1pm-2pm</p>\n<p><strong>O nline link</strong>:</p>\n<p><a href="https://gcc02.safelinks.protection.o utlook.com/?url=https%3A%2F%2Furldefense.us%2Fv3%2F__https%3A%2F%2Fteams.m icrosoft.com%2Fl%2Fmeetup-join%2F19*3ameeting_NzBkOThiY2UtN2NkYi00ODcxLThh OGItYWYyOWE4YTQ1NzY0*40thread.v2%2F0%3Fcontext%3D*7b*22Tid*22*3a*220cfca18 5-25f7-49e3-8ae7-704d5326e285*22*2c*22Oid*22*3a*22a8ae4553-86d9-421a-82d0- c175112acee8*22*7d__%3BJSUlJSUlJSUlJSUlJSUl!!G_uCfscf7eWS!faGZNgevT4W_ufn1 sHk4l_w3Kllw6CYpaShGFk_bggnWzgHq3LdKiott3ukX3ah3-9pHXoL9lFkiR16_JqFBSr7e1Q eYLFjFsw%24&amp\;data=05%7C02%7Cyili%40anl.gov%7C01b855f47ff14780e81e08df2 61c4f29%7C0cfca18525f749e38ae7704d5326e285%7C0%7C0%7C639271575166260823%7C Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJX aW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&amp\;sdata=Mwe9QI86l eIrgCcbyZe7Tobc4FzEfuZxTqoUCmW1xv0%3D&amp\;reserved=0">https://gcc02.safel inks.protection.outlook.com/?url=https%3A%2F%2Furldefense.us%2Fv3%2F__http s%3A%2F%2Fteams.microsoft.com%2Fl%2Fmeetup-join%2F19*3ameeting_NzBkOThiY2U tN2NkYi00ODcxLThhOGItYWYyOWE4YTQ1NzY0*40thread.v2%2F0%3Fcontext%3D*7b*22Ti d*22*3a*220cfca185-25f7-49e3-8ae7-704d5326e285*22*2c*22Oid*22*3a*22a8ae455 3-86d9-421a-82d0-c175112acee8*22*7d__%3BJSUlJSUlJSUlJSUlJSUl!!G_uCfscf7eWS !faGZNgevT4W_ufn1sHk4l_w3Kllw6CYpaShGFk_bggnWzgHq3LdKiott3ukX3ah3-9pHXoL9l FkiR16_JqFBSr7e1QeYLFjFsw%24&amp\;data=05%7C02%7Cyili%40anl.gov%7C01b855f4 7ff14780e81e08df261c4f29%7C0cfca18525f749e38ae7704d5326e285%7C0%7C0%7C6392 71575166260823%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjA uMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&amp \;sdata=Mwe9QI86leIrgCcbyZe7Tobc4FzEfuZxTqoUCmW1xv0%3D&amp\;reserved=0</a> </p>\n<p>&nbsp\;</p>\n<p><strong><span data-olk-copy-source="MessageBody"> Punchline:&nbsp\;</span></strong></p>\n<p>Leveraging fundamentally new ele ctronic structures\, back-end-of-line (BEOL) interconnects with novel cond uctors can revert the rising resistivity in nanoscale wiring and overcome the BEOL performance scaling bottleneck.</p>\n<p><strong>Abstract</strong> :</p>\n<p><span data-olk-copy-source="MessageBody">Resistivity of conventi onal metals\, such as Cu and Ru\, increases sharply below 20 nm. Consequen tly\, Cu interconnect scaling has become a key performance bottleneck in a dvanced-node integrated circuits. In this talk\, we first introduce the fu ndamentals for the interconnect technologies and discuss the root cause of the scaling bottleneck. We then explore how the resistivity increase can be mitigated or even reverted by adopting novel conductors\, namely\, topo logical and anisotropic conductors. From theoretical simulations to hardwa re demos\, we present the proof-of-concept verification of reversed resist ivity scaling using topological Cosi nanowires at 8&rdquo\; wafer scale\, showing that the predicted topological-surface-state physics can survive C MOS processing. We further survey the current research landscape and discu ss the urgent need for high-throughput screening with examples. We will co nclude with a list of requirements to help guide the search for best condu ctor candidates.</span></p> END:VEVENT END:VCALENDAR