BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT DTSTART:20270314T030000 TZOFFSETFROM:-0600 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20261026T031718Z UID:E1F847E3-CF6D-491A-AE7E-EFB2855C776F DTSTART;TZID=America/Chicago:20261120T150000 DTEND;TZID=America/Chicago:20261120T160000 DESCRIPTION:Computing Beyond Moore’s Law: From Heterogeneous Chiplets to 3D Adaptive Computing\n\nSpeaker: Prof. Yu [Kevin] Cao\, Dept. ECE\, Unive rsity of Minnesota\n\nAbstract:\n\nEnabled by advances in packaging techno logies\, the paradigm shift from monolithic integration to chiplet-based d esign is reshaping our computing systems\, from data centers to edge AI. C omposable chiplets offer scalable\, flexible\, and energy-efficient soluti ons for increasingly complex and heterogeneous workloads.\n\nThis talk pre sents our recent research on heterogeneous chiplet design and silicon prot otypes. We first introduce HISIM\, a simulation framework that integrates analytical models and machine-learning surrogates to evaluate power\, temp erature\, performance\, area\, and cost (PTPAC) across diverse computing u nits\, network topologies\, and memory hierarchies. Building upon HISIM\, we demonstrate a library of composable and reusable chiplets\, integrated with neural architecture search to enable Pareto-optimal co-design of AI m odels and hardware architectures.\n\nBeyond architectural optimization\, w e further introduce an emerging paradigm of 3D adaptive computing\, levera ging dense vertical interconnects to enable massively parallel data moveme nt and runtime hardware adaptation. By stacking distributed SRAM banks abo ve reconfigurable processing elements\, our 3D test chip in GF 22nm achiev es sub-microsecond full-chip reconfiguration\, over 1\,000× faster than c onventional FPGAs. This architecture combines ASIC-like efficiency with FP GA-like flexibility\, opening new opportunities for SWaP-constrained appli cations in robotics\, autonomous systems\, and edge AI.\n\nBio: Yu Cao rec eived the Ph.D. degree in electrical engineering from University of Califo rnia\, Berkeley\, in 2002. He is now the Louis John Schnell Professor of E lectrical and Computer Engineering at the University of Minnesota\, Minnea polis\, Minnesota. He has published numerous articles and three books on n ano-CMOS modeling and physical design. His research interests include neur al-inspired computing\, hardware-algorithm co-design\, and heterogeneous i ntegration. Dr. Cao was a Distinguished Lecturer of the IEEE Circuits and Systems Society. He was a recipient of seven Best Paper Awards and Outstan ding Researcher Awards from Intel\, IBM\, and others. He is a Fellow of th e IEEE.\n\nSpeaker(s): Prof. Yu [Kevin] Cao\, \n\nVirtual: https://events. vtools.ieee.org/m/589015 LOCATION:Virtual: https://events.vtools.ieee.org/m/589015 ORGANIZER:parhi@umn.edu SEQUENCE:24 SUMMARY:Computing Beyond Moore’s Law: From Heterogeneous Chiplets to 3D A daptive Computing URL;VALUE=URI:https://events.vtools.ieee.org/m/589015 X-ALT-DESC:Description: <br /><p>Computing Beyond Moore&rsquo\;s Law: From Heterogeneous Chiplets to 3D Adaptive Computing</p>\n<p>Speaker: Prof. Yu [Kevin] Cao\, Dept. ECE\, University of Minnesota</p>\n<p>Abstract:&nbsp\; </p>\n<p>Enabled by advances in packaging technologies\, the paradigm shif t from monolithic integration to chiplet-based design is reshaping our com puting systems\, from data centers to edge AI. Composable chiplets offer s calable\, flexible\, and energy-efficient solutions for increasingly compl ex and heterogeneous workloads.</p>\n<p>This talk presents our recent rese arch on heterogeneous chiplet design and silicon prototypes. We first intr oduce HISIM\, a simulation framework that integrates analytical models and machine-learning surrogates to evaluate power\, temperature\, performance \, area\, and cost (PTPAC) across diverse computing units\, network topolo gies\, and memory hierarchies. Building upon HISIM\, we demonstrate a libr ary of composable and reusable chiplets\, integrated with neural architect ure search to enable Pareto-optimal co-design of AI models and hardware ar chitectures.</p>\n<p><br>Beyond architectural optimization\, we further in troduce an emerging paradigm of 3D adaptive computing\, leveraging dense v ertical interconnects to enable massively parallel data movement and runti me hardware adaptation. By stacking distributed SRAM banks above reconfigu rable processing elements\, our 3D test chip in GF 22nm achieves sub-micro second full-chip reconfiguration\, over 1\,000&times\; faster than convent ional FPGAs. This architecture combines ASIC-like efficiency with FPGA-lik e flexibility\, opening new opportunities for SWaP-constrained application s in robotics\, autonomous systems\, and edge AI.</p>\n<p>Bio: Yu Cao rece ived the Ph.D. degree in electrical engineering from University of Califor nia\, Berkeley\, in 2002. He is now the Louis John Schnell Professor of El ectrical and Computer Engineering at the University of Minnesota\, Minneap olis\, Minnesota. He has published numerous articles and three books on na no-CMOS modeling and physical design. His research interests include neura l-inspired computing\, hardware-algorithm co-design\, and heterogeneous in tegration. Dr. Cao was a Distinguished Lecturer of the IEEE Circuits and S ystems Society. He was a recipient of seven Best Paper Awards and Outstand ing Researcher Awards from Intel\, IBM\, and others. He is a Fellow of the IEEE.</p> END:VEVENT END:VCALENDAR