BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Denver BEGIN:DAYLIGHT DTSTART:20270314T030000 TZOFFSETFROM:-0700 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:MDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20261027T072755Z UID:47D7433B-66E8-4172-A472-5C9847F88842 DTSTART;TZID=America/Denver:20261102T041000 DTEND;TZID=America/Denver:20261102T170000 DESCRIPTION:Circuits and Technology Advancements for Resiliency and Reliabi lity (11/02 -- 4:10PM )\nNext-generation SoCs for the Zetta-Scale computin g era will be developed with increased integration of our compute\, memory and communication systems in optimized advanced packaging solutions. The complexity of these systems is growing exponentially and the need to incre ase reliability while achieving high energy-efficiency is paramount. We wi ll explore the challenges and opportunities in technology and circuits to enable resilient\, reliable and secure circuits and systems. We will study several cases of advanced circuit design to address those growing challen ges.\n\nPresented by : Dr. Carlos Tokunaga\n\nCarlos Tokunaga (IEEE S’98 –M’08-SM’17) is a Senior Principal Engineer working in Technology an d Circuit Pathfinding at Intel Corporation. Carlos received the B.S. degre e in electronics engineering from the University of Los Andes\, Bogotá\, Colombia\, in 2001\, and the M.S. and Ph.D. degrees in electrical engineer ing from the University of Michigan\, Ann Arbor\, MI\, USA\, in 2005 and 2 008\, respectively. He is an IEEE Senior Member and served as a Member-at- Large in the IEEE SSCS Adcom in 2023-2025. He currently serves as the Gene ral Chair of CICC\, and is a TPC member of ISSCC. He served in the VLSI Sy mposium TPC 2019-2024. He serves as an Associate Editor for the Open Journ al of SSCS and is an SSCS Distinguished Lecturer 2025-2026. He received In tel Lab’s Gordon Moore Award in 2018. He has published over 55 technical papers in refereed conferences and journals and received over 20 patents. \n\nSpeaker(s): \, Carlos\n\nAgenda: \nCircuits and Technology Advancement s for Resiliency and Reliability (11/02 -- 4:10-5:00PM )\n\nQ&A with compl imentary snacks/drinks (5:00-5:30PM )\n\nVirtual: https://events.vtools.ie ee.org/m/589231 LOCATION:Virtual: https://events.vtools.ieee.org/m/589231 ORGANIZER:rsalazar@ieee.org SEQUENCE:31 SUMMARY:IEEE Albuquerque SSCS/EDS Chapter Talk: Circuits and Technology Adv ancements for Resiliency and Reliability URL;VALUE=URI:https://events.vtools.ieee.org/m/589231 X-ALT-DESC:Description: <br /><p><span style="color: rgb(0\, 0\, 0)\;"><spa n style="font-size: 18pt\; font-family: Aptos\; font-weight: bold\; font-s tyle: italic\;">Circuits and Technology Advancements for Resiliency and Re liability </span><span style="font-size: 18pt\; font-family: Aptos\; font- style: italic\;">(</span><span style="font-size: 18pt\; font-family: Aptos \; font-style: italic\;">11</span><span style="font-size: 18pt\; font-fami ly: Aptos\; font-style: italic\;">/</span><span style="font-size: 18pt\; f ont-family: Aptos\; font-style: italic\;">02</span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;"> </span><span style="fo nt-size: 18pt\; font-family: Aptos\; font-style: italic\;">-- </span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">4</sp an><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\ ;">:10PM </span><span style="font-size: 18pt\; font-family: Aptos\; font-s tyle: italic\;">)</span><span style="font-size: 18pt\; font-family: Aptos\ ; font-weight: bold\; font-style: italic\;"><br></span><span style="font-s ize: 14pt\; font-family: Aptos\;">Next-generation SoCs for the Zetta-Scale computing era will be developed with increased integration of our compute \, memory and communication systems in </span><u style="text-underline: si ngle\;"><span style="font-size: 14pt\; font-family: Aptos\;">optimized</sp an></u><span style="font-size: 14pt\; font-family: Aptos\;"> </span><u sty le="text-underline: single\;"><span style="font-size: 14pt\; font-family: Aptos\;">advanced packaging solutions</span></u><span style="font-size: 14 pt\; font-family: Aptos\;">. The complexity of these systems is growing ex ponentially and the need to increase reliability while achieving high ener gy-efficiency is paramount. We will explore the challenges and opportuniti es in technology and circuits to enable resilient\, reliable and secure ci rcuits and systems. We will study several cases of advanced circuit design to address those growing challenges.</span></span></p>\n<p>&nbsp\;</p>\n< p><span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 14pt\; fon t-family: Aptos\;"><img src="https://events.vtools.ieee.org/vtools_ui/medi a/display/dfb97975-0972-433b-8a4e-a90120746e47" width="222" height="222">< /span></span></p>\n<p>&nbsp\;</p>\n<p style="language: en-US\; line-height : 90%\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-ind ent: 0in\; text-align: left\; direction: ltr\; unicode-bidi: embed\; verti cal-align: baseline\; mso-line-break-override: restrictions\; punctuation- wrap: simple\;"><span style="color: rgb(0\, 0\, 0)\;"><span style="font-si ze: 16pt\; font-family: Tahoma\; font-style: italic\;">Presented </span><s pan style="font-size: 16pt\; font-family: Tahoma\; font-style: italic\;">b y</span><span style="font-size: 16pt\; font-family: Tahoma\; font-style: i talic\;"> </span><span style="font-size: 16pt\; font-family: Tahoma\; font -weight: bold\;">: </span><span style="font-size: 16pt\; font-family: 'Int elOne Text Light'\; font-weight: bold\; font-style: italic\;">Dr. </span>< span style="font-size: 16pt\; font-family: 'IntelOne Text Light'\; font-we ight: bold\; font-style: italic\;">Carlos Tokunaga</span></span></p>\n<p>< span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 14pt\; font-f amily: Aptos\;"><span style="font-size: 12pt\; font-family: 'IntelOne Text Light'\;">Carlos Tokunaga (IEEE S&rsquo\;98&ndash\;M&rsquo\;08-SM&rsquo\; 17) is a Senior Principal Engineer working in Technology and Circuit Pathf inding at Intel Corporation. Carlos received the B.S. degree in electronic s engineering from the University of Los Andes\, Bogot&aacute\;\, Colombia \, in 2001\, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan\, Ann Arbor\, MI\, USA\, in 2005 and 2008\, re spectively. He is an IEEE Senior Member and served as a Member-at-Large in the IEEE SSCS Adcom in 2023-2025. He currently serves as the General Chai r of </span><span style="font-size: 12pt\; font-family: 'IntelOne Text Lig ht'\;">CICC\, and</span><span style="font-size: 12pt\; font-family: 'Intel One Text Light'\;"> is a TPC member of ISSCC. He served in the VLSI Sympos ium TPC 2019-2024. He serves as an Associate Editor for the Open Journal o f SSCS and is an SSCS Distinguished Lecturer 2025-2026. He received Intel Lab&rsquo\;s Gordon Moore Award in 2018. He has published over 55 technica l papers in refereed conferences and journals and received over 20 patents .</span></span></span></p><br /><br />Agenda: <br /><p><span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-family: Aptos\; fon t-weight: bold\; font-style: italic\;">Circuits and Technology Advancement s for Resiliency and Reliability </span><span style="font-size: 18pt\; fon t-family: Aptos\; font-style: italic\;">(</span><span style="font-size: 18 pt\; font-family: Aptos\; font-style: italic\;">11</span><span style="font -size: 18pt\; font-family: Aptos\; font-style: italic\;">/</span><span sty le="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">02</span> <span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;"> </span><span style="font-size: 18pt\; font-family: Aptos\; font-style: it alic\;">-- </span><span style="font-size: 18pt\; font-family: Aptos\; font -style: italic\;">4</span><span style="font-size: 18pt\; font-family: Apto s\; font-style: italic\;">:10-5:00PM </span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">)</span></span></p>\n<p><span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-family : Aptos\; font-weight: bold\; font-style: italic\;">Q&amp\;A&nbsp\; with c omplimentary snacks/drinks </span><span style="font-size: 18pt\; font-fami ly: Aptos\; font-style: italic\;">(</span><span style="font-size: 18pt\; f ont-family: Aptos\; font-style: italic\;"><span style="font-size: 18pt\; f ont-family: Aptos\; font-style: italic\;">5</span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">:00-5:30PM </span>)</spa n></span></p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR