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DESCRIPTION:Fabrication of atomic-scale dopant-in-silicon for silicon quant
 um processors\n\nAbstract:\n\nAtomic-scale devices made from individual do
 pant atoms in silicon offer new ways to investigate physical phenomena and
  develop novel technologies.\n\nAt Asentas Quantum Systems (AQS)\, we are 
 developing a solid-state quantum processor architecture in which the valen
 ce electron of a single dopant atom serves as a spin qubit and the nuclear
  spin of the same atom is used as a quantum memory. I will introduce this 
 architecture and describe the fabrication technology that underpins it.\n\
 nOur approach uses scanning tunneling microscopy hydrogen resist lithograp
 hy (STM-HRL) to place individual dopant atoms deterministically with atomi
 c-scale precision. Although STM-HRL is an established technique\, the limi
 ted yield of single-atom fabrication has until recently been a major barri
 er scaling to large numbers of devices. I will show how we have overcome t
 his limitation\, achieving a single-atom yield approaching 100% for arseni
 c in silicon\, providing a fabrication pathway to qubit scaling [1\,2].\n\
 nI will outline the full device fabrication process and present preliminar
 y electrical measurements from arsenic-in-silicon devices fabricated using
  hydrogen resist lithography.\n\nFinally\, I will set out AQS’s vision f
 or building a fault-tolerant quantum computer.\n\nRead More:\n\n[Single-At
 om Control of Arsenic Incorporation in Silicon for High-Yield Artificial L
 attice Fabrication](https://advanced.onlinelibrary.wiley.com/doi/full/10.1
 002/adma.202312282)\n\n[Atomic-Scale Patterning of Arsenic in Silicon by S
 canning Tunneling Microscopy](https://pubs.acs.org/ancac3/article/14/3/331
 6/1389671/Atomic-Scale-Patterning-of-Arsenic-in-Silicon-by)\n\nAGENDA:\n\n
 Thursday November 12\, 2026\n\n11:30 AM: Networking\, Pizza &amp; Drinks\n\nNo
 on -- 1 pm: Seminar\n\nPlease register on Eventbrite before 9:30 AM on Thu
 rsday November 12\, 2026\n\n$4 IEEE members $6 non IEEE members\n\n(discou
 nts for unemployed and students )\n\nBldg: ==&gt; Use corner entrance: Kifer 
 Road / San Lucar Court ==&gt; Do not enter at main entrance on Kifer Road\, E
 AG Labs\, 810 Kifer Road\, Sunnyvale\, California\, California\, United St
 ates\, 95051
LOCATION:Bldg: ==&gt; Use corner entrance: Kifer Road / San Lucar Court ==&gt; Do
  not enter at main entrance on Kifer Road\, EAG Labs\, 810 Kifer Road\, Su
 nnyvale\, California\, California\, United States\, 95051
ORGANIZER:G.M.Friedman@ieee.org
SEQUENCE:41
SUMMARY:Fabrication of atomic-scale dopant-in-silicon quantum processors
URL;VALUE=URI:https://events.vtools.ieee.org/m/590146
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 &quot;&gt;\n&lt;h3&gt;&lt;span style=&quot;font-size: 24pt\;&quot;&gt;&lt;strong&gt;Fabrication of atomic-scal
 e dopant-in-silicon for silicon quantum processors&lt;/strong&gt;&lt;/span&gt;&lt;/h3&gt;\n&lt;
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 more details about your event. You can include things to know\, venue info
 rmation\, accessibility options&amp;mdash\;anything that will help people know
  what to expect.&quot;&gt;\n&lt;div class=&quot;Section-module__SectionContainer___fNm4Y&quot;&gt;
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 h3&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;strong&gt;Atomic-scale devices made from 
 individual dopant atoms in silicon offer new ways to investigate physical 
 phenomena and develop novel technologies.&lt;/strong&gt;&lt;/span&gt;&lt;/h3&gt;\n&lt;h3&gt;&lt;span 
 style=&quot;font-size: 18pt\;&quot;&gt;&lt;strong&gt;At Asentas Quantum Systems (AQS)\, we ar
 e developing a solid-state quantum processor architecture in which the val
 ence electron of a single dopant atom serves as a spin qubit and the nucle
 ar spin of the same atom is used as a quantum memory. I will introduce thi
 s architecture and describe the fabrication technology that underpins it.&lt;
 /strong&gt;&lt;/span&gt;&lt;/h3&gt;\n&lt;h3&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;strong&gt;Our appr
 oach uses scanning tunneling microscopy hydrogen resist lithography (STM-H
 RL) to place individual dopant atoms deterministically with atomic-scale p
 recision. Although STM-HRL is an established technique\, the limited yield
  of single-atom fabrication has until recently been a major barrier scalin
 g to large numbers of devices. I will show how we have overcome this limit
 ation\, achieving a single-atom yield approaching 100% for arsenic in sili
 con\, providing a fabrication pathway to qubit scaling [1\,2].&lt;/strong&gt;&lt;/s
 pan&gt;&lt;/h3&gt;\n&lt;h3&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;strong&gt;I will outline the 
 full device fabrication process and present preliminary electrical measure
 ments from arsenic-in-silicon devices fabricated using hydrogen resist lit
 hography.&lt;/strong&gt;&lt;/span&gt;&lt;/h3&gt;\n&lt;h3&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;stron
 g&gt;Finally\, I will set out AQS&amp;rsquo\;s vision for building a fault-tolera
 nt quantum computer.&lt;/strong&gt;&lt;/span&gt;&lt;/h3&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;h3&gt;&lt;span style
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 .com/doi/full/10.1002/adma.202312282&quot; href=&quot;https://advanced.onlinelibrary
 .wiley.com/doi/full/10.1002/adma.202312282&quot; target=&quot;_blank&quot; rel=&quot;nofollow 
 noopener noreferrer ugc&quot;&gt;&lt;strong&gt;Single-Atom Control of Arsenic Incorporat
 ion in Silicon for High-Yield Artificial Lattice Fabrication&lt;/strong&gt;&lt;/a&gt;&lt;
 /span&gt;&lt;/h3&gt;\n&lt;h3&gt;&lt;br&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;a title=&quot;https://pub
 s.acs.org/ancac3/article/14/3/3316/1389671/Atomic-Scale-Patterning-of-Arse
 nic-in-Silicon-by&quot; href=&quot;https://pubs.acs.org/ancac3/article/14/3/3316/138
 9671/Atomic-Scale-Patterning-of-Arsenic-in-Silicon-by&quot; target=&quot;_blank&quot; rel
 =&quot;nofollow noopener noreferrer ugc&quot;&gt;&lt;strong&gt;Atomic-Scale Patterning of Ars
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 \n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/form&gt;&lt;/div&gt;\n&lt;/div&gt;\n&lt;/section
 &gt;\n&lt;/main&gt;&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n
 &lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;d
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 dex=&quot;0&quot; role=&quot;button&quot; data-testid=&quot;AboutThisEventSection&quot; aria-label=&quot;Over
 view. Use this section to provide more details about your event. You can i
 nclude things to know\, venue information\, accessibility options&amp;mdash\;a
 nything that will help people know what to expect.&quot;&gt;\n&lt;div id=&quot;AboutThisEv
 entPreview&quot; class=&quot;css-1dykrq ezg9ojv5&quot; data-testid=&quot;AboutThisEventPreview
 &quot;&gt;\n&lt;div data-testid=&quot;ModulesListPreview&quot;&gt;\n&lt;div class=&quot;css-1hbyxwu e1pmrt
 pl0&quot;&gt;\n&lt;p&gt;&lt;strong&gt;Thursday November 12&lt;/strong&gt;&lt;strong&gt;\, 2026&lt;/strong&gt;&lt;/p
 &gt;\n&lt;p&gt;&lt;strong&gt;11:30 AM: Networking\, Pizza &amp;amp\; Drinks&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;
 &lt;strong&gt;Noon -- 1 pm: Seminar&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Please register on 
 Eventbrite before 9:30 AM on&lt;/strong&gt;&lt;strong&gt; Thursday November 12\, 2026&lt;
 /strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;$4 IEEE members&amp;nbsp\; $6 non IEEE members &lt;/stro
 ng&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;(discounts for unemployed and students&lt;/strong&gt; )&lt;/p&gt;\
 n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;
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