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DTSTART:20100314T030000
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DTSTAMP:20110218T234511Z
UID:EE2FBDC3-E5B6-11E7-833E-0050568D7F66
DTSTART;TZID=Canada/Eastern:20100416T140000
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DESCRIPTION:High frequency jitter tracking in high speed I/Os is beneficial
  for several reasons including burst mode functionality for power reductio
 n. However\, providing such high tracking bandwidth in power and area effi
 cient way is challenging. In a clock forwarded receiver the clock path in 
 a 65nm CMOS receiver comprises two injection-locked oscillators to frequen
 cy-multiply\, deskew\, and track correlated jitter on a pulsed clock forwa
 rded from the transmitter. Latency mismatch and data rates are accommodate
 d by controlling jitter tracking up to 300MHz. Each receiver consumes 0.92
 pJ/b at 7.4Gb/s with a jitter tolerance of 1.5UI at 200MHz. Similarly\, in
  a clock embedded receiver high frequency jitter can be provided with a ha
 lf rate injection locked oscillator. The clock recovery technique is verif
 ied with experimental results at 5-10 Gb/s 90 nm CMOS\, consuming 70 mW an
 d acquiring lock within 1.5 n\n\nWaterloo\, Ontario\, Canada
LOCATION:Waterloo\, Ontario\, Canada
ORGANIZER:
SEQUENCE:0
SUMMARY:[Legacy Report] Burst Mode Power Efficient High Speed Receivers in 
 CMOS
URL;VALUE=URI:https://events.vtools.ieee.org/m/59646
X-ALT-DESC:Description: <br />High frequency jitter tracking in high \nspee
 d I/Os is beneficial for several \nreasons including burst mode \nfunction
 ality for power reduction. \nHowever\, providing such\n high tracking \nba
 ndwidth in power and area efficient \nway is challenging. In a clock forwa
 rded \nreceiver the clock path in a 65nm CMOS \nreceiver comprises two\n i
 njection-locked \noscillators to frequency-multiply\, \ndeskew\, and track
  correlated jitter on a \npulsed clock forwarded from the \ntransmitter. L
 atency mismatch and data\n \nrates are accommodated by controlling \njitte
 r tracking up to 300MHz. Each \nreceiver consumes 0.92pJ/b at 7.4Gb/s \nwi
 th a jitter tolerance of 1.5UI at \n200MHz.\n Similarly\, in a clock embed
 ded \nreceiver high frequency jitter can be \nprovided with a half rate in
 jection \nlocked oscillator. The clock recovery \ntechnique is verified wi
 th\nexperimental \nresults at 5-10 Gb/s 90 nm CMOS\, \nconsuming 70 mW and
  acquiring lock \nwithin 1.5 n
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