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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Calcutta
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20130916T103016Z
UID:EFEDC5F5-E5B6-11E7-833E-0050568D7F66
DTSTART;TZID=Asia/Calcutta:20130817T090000
DTEND;TZID=Asia/Calcutta:20130818T170000
DESCRIPTION:Joint Chapter of Circuits and Systems and Electron Devices Soci
 eties (CAS/EDS)in collaboration with Muffakham Jah College of Engineering 
 and Technology organised a Two Day Workshop by Industry Professionals on S
 oC Design on 17th and 18th August\, 2013.This workshop aims at discussing 
 process of taking a SoC design from the original specification to the fina
 l product i.e. Architecture\, Design & Verification\, Implementation & Phy
 sical Design and finally Test & Validation of SoC\, with respect to an App
 lication Processor\n\nCo-sponsored by: Muffakham Jah College of Engineerin
 g and Technology\n\nSpeaker(s): Balaji kanigicherla\, Anand Moghe\n\nHyder
 abad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:arif.sohel@gmail.com
SEQUENCE:0
SUMMARY:[Legacy Report] Two Day workshop on SoC Design
URL;VALUE=URI:https://events.vtools.ieee.org/m/91671
X-ALT-DESC:Description: <br />Joint Chapter of Circuits and Systems and Ele
 ctron Devices Societies (CAS/EDS)in collaboration with Muffakham Jah Colle
 ge of Engineering and Technology organised a Two Day Workshop by Industry 
 Professionals on SoC Design on 17th and 18th August\, 2013.This workshop a
 ims at discussing process of taking a SoC design from the original specifi
 cation to the final product i.e. Architecture\, Design & Verification\, Im
 plementation & Physical Design and finally Test & Validation of SoC\, with
  respect to an Application Processor
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