Image Processing in VHDL on FPGAs
Joint Massey University / IEEE NZ Central Section Workshop
Field Programmable Gate Arrays (FPGAs) are increasingly being used as an implementation platform for real-time embedded image processing applications because their architecture is able to exploit spatial and temporal parallelism. Unfortunately, simply porting an algorithm onto an FPGA often gives disappointing results, because most image processing algorithms have been optimised for a serial processor. Therefore it is necessary to transform the algorithm to efficiently exploit the parallelism inherent within the algorithm. This course introduces a design approach for FPGA
based imaging system development, highlighting the significant differences between hardware and software based design. Through lectures and
hands-on laboratories, the basic tools for FPGA based development are introduced, and used for implementing a range of fundamental image
processing operations.
Date and Time
Location
Hosts
Registration
- Start time: 04 Apr 2018 09:00 AM
- End time: 06 Apr 2018 05:00 PM
- All times are (GMT+12:00) NZ
-
Add Event to Calendar
- Palmerston North, North Island
- New Zealand
- Contact Event Host
- Co-sponsored by Massey University
Speakers
Donald Bailey
Biography:
Professor Donald Bailey has over 35 years of experience in image processing and machine vision. Over the last 15 years he has conducted extensive research in mapping image processing algorithms onto FPGAs. He is the author of many publications in this field, including the book “Design for Embedded Image Processing on FPGAs.”
Email:
Address:School of Engineering and Advanced Technology, Massey University, Palmerston North, New Zealand