Distinguished Lecturer Seminar by Prof. Gabor C. Temes: "A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC"

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"A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC"

Prof. Gabor C. Temes, School of EECS, Oregon State University

on Thursday July 26th, 2018

IEEE Santa Clara Valley Section

PROGRAM

6:00 - 6:30 PM Networking & Refreshments
6:30 - 7:45 PM Talk
7:45 - 8:00 PM Q&A/Adjourn

Watch the lecture live on Zoom from your home and anywhere around the world! Register now and you will be sent details one day before the event.

Abstract:

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatcherror can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping.

Bio:

Gabor C. Temes received the Ph.D. degree in Electrical Engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991.

He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

Venue:

Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

Convenient VTA light rail access from Mountain View and downtown San Jose.

Live Broadcast:

Lecture will be broadcast live on Zoom. Registrants will be sent the conference details one day before the event. See zoom instructions here: ZoomInstructions.

Admission Fee:

Open to all to attend 
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!



  Date and Time

  Location

  Contact

  Registration


  • Cypress Semiconductor Corporation
  • 198 Champion Ct
  • San Jose, California
  • United States 95134
  • Building: Main Auditorium in Building 6
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=37.4102163%2c 121
  • Co-sponsored by Solid State Circuits Society (SSCS)


  Speakers

Gabor Temes of School of EECS, Oregon State University

Topic:

Distinguished Lecturer Seminar by Prof. Gabor C. Temes: "A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC"

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much  smaller  than  that  of  the conventional binary-weighted capacitor array, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the   proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping.

Biography:

Gabor C. Temes received the Ph.D. degree in electrical engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991.

He held academic positions at the Technical University of Budapest, Stanford University  and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.





Agenda

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much  smaller  than  that  of  the conventional binary-weighted capacitor array, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the   proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping.