Adaptive and Resilient Circuits for Improving Processor Performance, Energy Efficiency, and Yield
Dynamic device, circuit, and system parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large CPUs in multicore servers. This seminar introduces the primary variations during the processor operational lifetime, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations. This presentation then describes the negative impact of these variations on processor performance, energy efficiency, and yield. The wide dynamic voltage-frequency scaling (DVFS) range in today’s processors increases these effects. For future IoT edge processors, the low-cost packaging, voltage regulation with time-varying energy harvesters, wide temperature range, and long-lifetime requirements exacerbate these problems further. To mitigate the adverse effects from dynamic variations, this seminar presents adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment.
Date and Time
Location
Hosts
Registration
- Date: 07 Nov 2018
- Time: 10:00 AM to 11:45 AM
- All times are (UTC-08:00) Pacific Time (US & Canada)
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- Qualcomm Q Auditorium (6455 Lusk Blvd, San Diego, CA 92121)
- San Diego, California
- United States
- Contact Event Host
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Non-Qualcomm Employees:
If you plan to attend, please send an email to aloke@qti.qualcomm.com and indicate your Name, Affiliation, Email, and Country of Citizenship by Monday 10/29. This will help expedite getting your visitor badge. Please come 10-15 minutes earlier to find parking. Proceed to the front lobby of Building Q to sign in as a visitor.
- Starts 30 October 2018 05:14 PM
- Ends 06 November 2018 05:14 PM
- All times are (UTC-08:00) Pacific Time (US & Canada)
- No Admission Charge
Speakers
Keith Bowman
Adaptive and Resilient Circuits for Improving Processor Performance, Energy Efficiency, and Yield
Dynamic device, circuit, and system parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large CPUs in multicore servers. This seminar introduces the primary variations during the processor operational lifetime, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations. This presentation then describes the negative impact of these variations on processor performance, energy efficiency, and yield. The wide dynamic voltage-frequency scaling (DVFS) range in today’s processors increases these effects. For future IoT edge processors, the low-cost packaging, voltage regulation with time-varying energy harvesters, wide temperature range, and long-lifetime requirements exacerbate these problems further. To mitigate the adverse effects from dynamic variations, this seminar presents adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment.
Agenda
10:00-10:15 Sign-in and networking
10:15-11:45 Seminar (with Q&A after seminar)