The MIPS I6500-F Microprocessor - Functional Safety for ADAS Applications

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A High Plains Section Sponsored Event

 


The MIPS I6500-F Microprocessor - Functional Safety for ADAS Applications

Autonomous driving and other emerging applications of Artificial Intelligence demand increasing levels of computing performance in safety-critical systems.  Chip companies address this market by building System-on-Chip (SoC) designs around compute engines such as CPUs, DSPs, GPUs and application-specific accelerators, which are often sourced from third-party suppliers in the form of RTL-level synthesizable IP.  Designing a synthesizable CPU IP for functional safety (and obtaining certification to standards such as ISO 26262) presents some unique challenges.  This talk gives an overview of the MIPS I6500-F microprocessor design, its application to ADAS applications, and the ISO 26262 certification process.

 

 



  Date and Time

  Location

  Contact

  Registration



  • DeskChair workspace
  • 201 East 4th Street
  • Loveland, Colorado
  • United States 80537
  •  

     

  • Co-sponsored by jlagrotta@gmail.com
  • Starts 16 December 2018 06:13 AM
  • Ends 20 March 2019 12:00 PM
  • All times are US/Mountain
  • No Admission Charge


  Speakers

Philip McCoy

Topic:

The MIPS I6500-F Microprocessor - Functional Safety for ADAS Applications

Abstract:
The MIPS I6500-F Microprocessor - Functional Safety for ADAS Applications

Autonomous driving and other emerging applications of Artificial Intelligence demand increasing levels of computing performance in safety-critical systems.  Chip companies address this market by building System-on-Chip (SoC) designs around compute engines such as CPUs, DSPs, GPUs and application-specific accelerators, which are often sourced from third-party suppliers in the form of RTL-level synthesizable IP.  Designing a synthesizable CPU IP for functional safety (and obtaining certification to standards such as ISO 26262) presents some unique challenges.  This talk gives an overview of the MIPS I6500-F microprocessor design, its application to ADAS applications, and the ISO 26262 certification process.

Biography:

Philip McCoy is a Principal IC Design Engineer in Wave Computing's MIPS business unit, where he is the lead designer for the I6500 mid-range multi-threaded multiprocessor CPU IP product family.

Philip started his career in the PA-RISC microprocessor design team at HP, followed by several years in the digital TV SoC team at Philips Semiconductors.  Since joining MIPS in 2005, he has lead design and verification efforts spanning the CPU product range, as MIPS navigated major corporate transitions including acquisitions by Imagination Technologies and Wave Computing.  He has been telecommuting from his Fort Collins home-office since 2012.

Philip received a BSEE from Grove City College, and an MSEE from Purdue University.  He is a classroom volunteer at Coyote Ridge Elementary School.  In his free time, he enjoys hanging out with his family and teaching his son more than any 9-year-old wants to know about microprocessors.





Agenda

6:00-6:30 pm Networking Time

6:30-6:45 business Meeting

6:45 -8:30 Main Presentation