IEEE@SFSU Intel Workshop - Introduction to Digital High Level Design Workshop
The VHDL and Verilog hardware description languages have been the standard-bearers for describing digital circuitry for several decades. Recently, a new class of “C” like languages have come to the forefront of describing parallel computationally intensive workloads to speed up development of FPGAs. These languages describe comparable workloads in a fraction of the lines of code, and require less knowledge of digital electronics hardware. This workshop will describe the HLS (High Level Synthesis) language and give software and hardware engineers an appreciation for the efficiency of coding computationally intense algorithms used for AI, Machine Learning and Vision Processing. Pre-requisites: A course in “C” or “C++” and a course in Digital Logic design with some knowledge of VHDL and/or Verilog are required for this workshop.
Date and Time
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- Date: 23 Apr 2019
- Time: 09:00 PM UTC to 12:30 AM UTC
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- San Francisco, California
- United States
- Starts 16 April 2019 01:00 AM UTC
- Ends 23 April 2019 08:50 PM UTC
- 3 in-person spaces left!
- No Admission Charge