Cryogenic CMOS for Qubit Control and Readout
Scaling a fault-tolerant quantum computer to millions of qubits required for running a practical algorithm is a daunting challenge. Substantial innovation is required in qubit fabrication, integration and control. CMOS integrated circuits operating at cryogenic temperature down to 4K can offer significantly higher system integration and enable scalability for future quantum computers. Complex System-on-Chips (SoCs) with digital, analog and RF capabilities can be integrated with sufficiently low power consumption to be compatible with the requirements of dilution refrigerators. This talk gives an overview of some of the control electronics requirements for spin qubits and details the design and measured results of two Intel cryogenic SoCs (Horse Ridge 1&2) designed to operate at 4K.
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- Date: 06 Oct 2022
- Time: 03:00 PM to 04:00 PM
- All times are (UTC-06:00) Central Time (US & Canada)
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Stefano Pellerano Ph.D. of intel
Cryogenic CMOS for Qubit Control and Readout
Scaling a fault-tolerant quantum computer to millions of qubits required for running a practical algorithm is a daunting challenge. Substantial innovation is required in qubit fabrication, integration and control. CMOS integrated circuits operating at cryogenic temperature down to 4K can offer significantly higher system integration and enable scalability for future quantum computers. Complex System-on-Chips (SoCs) with digital, analog and RF capabilities can be integrated with sufficiently low power consumption to be compatible with the requirements of dilution refrigerators. This talk gives an overview of some of the control electronics requirements for spin qubits and details the design and measured results of two Intel cryogenic SoCs (Horse Ridge 1&2) designed to operate at 4K.
Biography:
Stefano Pellerano was born in Bari, Italy, in 1977. He received the Laurea Degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respec-tively. During his Ph.D., his activity was focused on the design of fully integrated low-power frequency synthesiz-ers for WLAN applications. In 2003 he has been a consultant with Agere Systems (former Bell Labs) in Allen-town, PA. Since 2004 he has been with Intel Labs, in Hillsboro, OR. He is now Principal Engineer leading the Next Generation Radio Integration Lab, where he drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies. His main research contributions include MIMO transceivers for WiFi, digital PLLs, high-efficient digital architectures for polar and outphasing transmitters, mm-wave radio transceiver and phased-array systems, and low-power radios. In the last five years, he has also been exploring cryogenic CMOS integrated electronics for qubit control, leading to the development of “Horse Ridge”, Intel cryogenic qubit controller technology to address the interconnect bottleneck in future large-scale quantum com-puters. Stefano has authored or co-authored more than 50 IEEE conference and journal papers, one Nature paper, one book chapter and more than 25 issued patents. He was a co-recipient of ISSCC 2019 Lewis Winner Award for Outstanding Paper and ISSCC 2020 Jan Van Vessem Award for Outstanding European Paper. He served as a member of the ISSCC iTPC from 2014 to 2022, leading the Wireless Subcommittee from 2018 to 2022. He is currently serving as the Forum Chair for 2023 ISSCC. He also served as the Technical Program Chair and General Chair for the IEEE Radio Frequency Integrated Circuit (RFIC) Symposium in 2018 and 2019 respectively and he is now part of the RFIC Executive Committee.
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