16th Central Pennsylvania Symposium on Signal and Power Integrity
The Center for Signal Integrity at Penn State Harrisburg will host the 16th Central Pennsylvania Symposium on Signal/Power Integrity, Friday, April 28, 2023 from 8:00 a.m. to 4:30 p.m.
For more details on the talks/speakers please visit https://harrisburg.psu.edu/center-for-signal-integrity/symposium
Date and Time
Location
Hosts
Registration
- Date: 28 Apr 2023
- Time: 08:00 AM to 04:30 PM
- All times are (UTC-05:00) Eastern Time (US & Canada)
- Add Event to Calendar
- 777 West Harrisburg Pike
- Middletown, Pennsylvania
- United States 17057-4898
- Building: Library 101, Morrison Gallery
- Room Number: 101
- Click here for Map
- Contact Event Host
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Dr. Aldo Morales, awm2@psu.edu
Dr. Sedig Agili, ssa10@psu.edu
Mrs. Kelly Batche, klb68@psu.edu
- Co-sponsored by Penn State Harrisburg
- Starts 20 March 2023 08:00 AM
- Ends 28 April 2023 09:50 AM
- All times are (UTC-05:00) Eastern Time (US & Canada)
- Admission fee ?
Speakers
Dr. Mike Steinberger
Managing Differential Via Crosstalk and Return Via Placement
Biography:
Bio: Michael Steinberger, Ph.D. is a Consultant Software Engineer at MathWorks and has over 30 years of experience designing very high-speed electronic circuits.
Bill Hargin
Stackups: The Design Within the Design
Biography:
Bio: Bill Hargin is the chief everything officer at Z-zero LLC, developer of the PCB stackup design and material selection software, Z-planner Enterprise. Bill is an industry pioneer, with more than 25 years working in PCB signal integrity and manufacturing, while authoring dozens of articles on signal integrity, stackup design, and material selection.
Agenda
Program 16th Central Pennsylvania Symposium on Signal and Power Integrity For more details on the Talks/Speakers please visit https://harrisburg.psu.edu/center-for-signal-integrity/symposium/program |
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8:00 to 8:30 AM |
Registration April 28, 2023 |
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8:30 to 9:30 AM
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Welcoming Remarks Welcome and Plenary Speaker 1, Main Room Title: “Managing Differential Via Crosstalk and Return Via Placement” Dr. Mike Steinberger, MathWorks Bio: Michael Steinberger, Ph.D. is a Consultant Software Engineer at MathWorks and has over 30 years of experience designing very high-speed electronic circuits. |
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9:40 to 11:10 AM
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Workshop 1 Main room Intuitive Simulation and Measurement Workflow for Hardware Engineers By Joe Evangelista and OJ Danzy Keysight
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Workshop 2 Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0 Jason Ellison, Principal Technologist, Rohde & Schwarz Matt Burns, Marketing Director, SAMTEC Eric Oseassen, Applications Engineer, Rohde & Schwarz |
11:15 to 12:15 PM
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Plenary Speaker 2 Title: “Stackups: The Design Within the Design” Bill Hargin, Z-zero LLC Bio: Bill Hargin is the chief everything officer at Z-zero LLC, developer of the PCB stackup design and material selection software, Z-planner Enterprise. Bill is an industry pioneer, with more than 25 years working in PCB signal integrity and manufacturing, while authoring dozens of articles on signal integrity, stackup design, and material selection. |
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12:30 to 1:30 PM
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Plenary Speaker 3 Title: “Developing High-Quality Test Fixtures for De-embedding of S-Parameters” Dr. Jim Drewniak, President of Clear Signal Solutions Bio: Dr. Jim Drewniak is the Curator’s Professor Emeritus, Missouri S&T, EMC Laboratory, and President of Clear Signal Solutions, james.drewniak@clearsig.com |
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1:45 to 2:45 PM
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Plenary Speaker 4 Title:"VRM Modeling and Stability Analysis for the Power Integrity Engineer" Ben Dannan, Northrop Grumman. Bio: Benjamin Dannan is a technical fellow and an experienced signal and power integrity (SI/PI) design engineer, advancing high-performance ASIC and FPGA designs at Northrop Grumman. |
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2:50 to 4:20 PM
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Workshop 3 (Main Room) Leveraging Automation to Optimize Assemblies using Encrypted 3D Components By: Juliano Mologni, Lead SI/PI Product Manager, Ansys |
Workshop 4 Addressing PCIe 6.0 Design and Analysis Challenges By: Jared James, Sr Principal Product Engineer, Cadence
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