Designing Low-power “Intelligent” Chips in the face of Statistical Variations of Nanoscale Devices: The Neuromorphic Solution


IEEE Swiss CAS DLP Seminar by Prof. Arindam Basu, NTU Singapore

Title: Designing Low-power “Intelligent” Chips in the face of Statistical Variations of Nanoscale Devices: The Neuromorphic Solution



  Date and Time

  Location

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  Registration


  • Winterthurerstrasse 190
  • University of Zurich
  • Zurich, Switzerland
  • Switzerland 8057
  • Building: Y35
  • Room Number: F51

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  Speakers

Arindam Basu of NTU Singapore

Topic:

Designing Low-power “Intelligent” Chips in the face of Statistical Variations of Nanoscale Devices: The Neuromorphic Sol

As CMOS technology has been scaling down over the last decade, the effect of statistical variations (or component mismatch) and their impact on circuit design have become increasingly prominent. Further, new nanoscale devices like memristors and spin-mode devices like domain wall memories have emerged as possible candidates for neuromorphic computing at energy levels lower than CMOS—however, they also suffer from issues of variability and mismatch. In this talk, I will present some of the work done by our group where we take inspiration from neuroscience and show new approaches to perform machine learning with low-energy consumption using low-resolution mismatched components. First, I will talk about “combinatoric learning” using binary or 1-bit synapses—an alternative to weight based learning in neural networks that is inspired by structural plasticity in our brains. Second, I will present an example of utilizing component mismatch to perform part of the computation—an example of algorithm-hardware co-design involving random projection algorithms like Reservoir Computing or Extreme Learning Machine. Lastly, I will show an application of such a low-power machine learner to perform intention decoding in low-power brain-machine interfaces.

Biography:

Arindam Basu received the B.Tech and M.Tech degrees in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur in 2005, the M.S. degree in Mathematics and PhD. degree in Electrical Engineering from the Georgia Institute of Technology, Atlanta in 2009 and 2010 respectively. Dr. Basu received the Prime Minister of India Gold Medal in 2005 from I.I.T Kharagpur (awarded to the top student). In the summer of 2008, he worked at Texas Instruments, Dallas and developed automatic tuning strategies for LNAs designed in 45nm and 65nm. He joined Nanyang Technological University as an Assistant professor in June 2010. He is currently an Associate Editor of IEEE Sensors journal (2015-17) and IEEE Transactions on Biomedical Circuits and Systems (2016-18). He is a technical committee member of the IEEE CAS societies of Biomedical Circuits and Systems, Neural Systems and Applications (Secretary Elect) and Sensory Systems.