Tutorial on Low Power Methodologies, Techniques, and Tools
#low
#power
#integrated
#circuits
#biomedical
#devices
This 2-day tutorial will focus on low power design circuits and systems, including techniques, tools and methodologies.
Dates:
September 7-8, 2017, 8:00 a.m. to 16:00 p.m.
Topics:
- Low Power Design, Systems and Applications.
- Low Power Features of IC and Systems.
- Low Power Design Methodologies
- Power Integrity of Boards and Interconnects
Date and Time
Location
Hosts
Registration
- Start time: 07 Sep 2017 08:00 AM
- End time: 08 Sep 2017 04:30 PM
- All times are (GMT-06:00) America/Costa_Rica
-
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- Instituto Tecnológico de Costa Rica
- Cartago, Cartago
- Costa Rica 30101
- Building: k1, Electronics Engineering
- Starts 25 August 2017 12:00 AM
- Ends 07 September 2017 08:00 AM
- All times are (GMT-06:00) America/Costa_Rica
- 4 in-person spaces left!
- No Admission Charge
Agenda
Technical Program:
Thursday 7 Sept.
| Presenters | Topic | Schedule |
| Maria J. Quiros, Intel Costa Rica | Low Power Essentials | 9:00-10:00 |
| Jose E. Campos Murillo, Marco Espinoza, Intel Costa Rica | Power management features in Intel processors | 10:30-11:30
|
| Juan M. Sanchez Corrales, Intel Costa Rica | Scalable methodology to measure power on a HPC cluster | 13:00-14:00 |
| Martin Peterburg Alzaradel, Julio Soto Benavides. Intel Costa Rica | Power Integrity Techniques for Optimized Power Consumption & Performance | 14:30-15:30 |
Friday 8 Sept.
| Presenters | Topic | Schedule |
| Dr. Alfredo Arnaud, UCU, Uruguay | Ultra Low Power VLSI Analog Design for IMDs | 8:00-11:30, with coffee-break |
| Dr. Elkim Roa, Onchip UIS, Colombia
|
5-10 Gbs low-power SOC Interfaces based on RISC-V | 13:00-16:30, with coffee-brea |