Heterogeneous integration of III-V nanowires on Group IV substrates and applications
III-V compound semiconductor nanowires (NWs) have been attracted much attention as alternative materials for future electronics and optics. Heterogeneous integration of the vertical III-V NWs is important for the device applications. The selective-area growth achieved to align vertical III-V NWs on Si by making As-incorporated Si(111) 1´1 surface and to form modulation-doped core-multishell (CMS), axial QD nuclei and CMS double heterostructures. Here we report on recent progress in selective-area growth of III-V NWs on Si and their applications such as light-emitting diodes (LEDs), field-effect transistors (FETs), and tunnel FETs (TFETs) using III-V/Si heterojunctions.
III-V nanowires (NWs) with CMS double heterostructure integrated on Si platform are promising materials as vertical TFET application. There are still challenges in using TFETs for building energy-efficient circuits application, which requires a moderately high conductance and steep SS for several decades of currents. This means high quality tunnel junctions should be further designed for satisfying these requirements for future ICs. A level of scalability and complementary switching similar to that of conventional FETs must also be assured. We present a vertical gate-all-around (VGAA) TFET that uses our designed vertical InGaAs NW/Si heterojunction with modulation doped CMS NW and demonstrate steep subthreshold slope as well as enhancement of tunnelling current. And I will introduce current project for next-generation electronics and photonics.
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- Research School of Physics
- 60 Mills Rd, Acton
- Canberra, Australian Capital Territory
- Australia 2601
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- Co-sponsored by Department of Electronic Materials Engineering, Research School of Physics, The Australian National University.